View DS1991_1394350.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

a analog devices inc., proprietary & confidential 6/5/98 rev 2.1 - information subject to change page 1 of 74 a a single-chip, dsp-based high performance motor controller p reliminary t echnical i nformation admc401 f eatures 26 mips fixed point dsp core single cycle instruction execution (38.5 ns). external 14-bit address and 24-bit data bus. adsp-21xx family code compatible. 16-bit arithmetic & logic unit (alu). hardware multiply & accumulate unit (mac). single cycle 16-bit x 16-bit multiply & accumulate into 40-bit accumulator. 32-bit shifter (logical & arithmetic). multifunction instructions. single cycle context switch. powerful program sequencer: zero overhead looping. conditional instruction execution. two independent data address generators. memory configuration 2k x 24-bit internal program memory ram. 2k x 24-bit internal program memory rom. 1k x 16-bit internal data memory ram. address & data buses permit external memory expansion. high-resolution multichannel adc system 12-bit analog to digital converter. pipeline flash architecture. 8 dedicated analog inputs. all 8 channels converted in <2 m s. channels sampled at 120 ns intervals. 8 dedicated, memory-mapped, 16-bit, 2?s complement data registers. 4.0 v peak-peak input voltage range. ability to synchronize conversions to pwm. internal or external convert start. differential non li nearity < 1 lsb. integral non linearity < 2 lsb. dedicated adc interrupt on end of conversion. operation from internal or external reference. voltage reference internal 2.5 v 1.0 % voltage reference. dedicated vref pin. three-phase pwm generation subsystem 16-bit dedicated pwm generator. edge resolution to 38.5 ns. programmable dead time. programmable minimum pulse width. double update mode allows duty cycle & period adjustment on half cycle boundaries. special features for brushless dc & switched reluctance motors. hardware polarity control. external dedicated asynchronous shutdown pin ( pwmtrip ). additional shutdown pins in i/o system. individual enable/disable of each output. high-frequency chopping mode. transparent transition to over-modulation range with duty cycles of 100%. capability to drive optocouplers directly (10 ma sink & source capability). flexible encoder interface subsystem incremental encoder interface. dedicated interface (quadrature and index signals). a lternative frequency and direction inputs. programmable filtering of encoder input signals. glitch detection. 16-bit quadrature counter. input encoder signals to 3.25 mhz. programmable maxcnt register. two inputs permit latching of encoder counter value on external triggers. optional hardware reset of counter.
a a admc401 - p reliminary t echnical i nformation a analog devices inc., proprietary & confidential 6/5/98 rev 2.1 - information subject to change page 2 of 74 single north marker mode: permits single reset of counter on only first zero marker. status bits to read encoder inputs. companion encoder event system for accuracy enhancements at low speeds. associated eiu loop timer permits regular, programmable updating of all encoder and event timer registers. eiu timer can also be used as general purpose timer if not linked to eiu block. peripheral i/o (pio) subsystem 12 pin digital i/o port. bit configurable as input or output. each pin configurable as rising edge, falling edge, high level or low level interrupt. hysteresis on all pio input lines. four dedicated pio interrupts on pio0 to pio3. one combined interrupt for pio4 to pio11. each i/o line configurable as pwm trip source. two 8-bit auxiliary pwm outputs fixed 50.7 khz switching frequency. 0 to 99.6 % duty cycle. event timer unit two event timer channels (capture) accurate timing of duty-cycle, period and frequency. flexible event definition for configuration. event timer readable on-the-fly programmable interrupt controller manages priority & masking of peripheral interrupts. 16-bit watchdog timer dedicated clock source derived from clkin. internal power-on reset system monitors supply voltage during operation. programmable 16-bit interval timer with prescaler two double buffered synchronous serial ports variety of boot load protocols via sport1: synchronous e 2 prom/srom booting. uart boot loader with autobaud. synchronous master or slave boot loader. debugger interface via sport1: uart interface with autobaud. synchronous master or slave interface. rom utilities full debugger for program development. pre-programmed math functions: sine function. cosine function. arctan function. sqrt function. log10 and ln functions. reciprocal function. unsigned single precision division. umask - limit unsigned value. smask - limit signed value. fltone - fixed-point (1.15) to two-word floating-point conversion. fixone - two-word floating-point to fixed-point (1.15) conversion. fpa - two-word floating-point addition. fps - two-word floating-point subtraction. fpm - two-word floating-point multiplication. fpd - two-word floating-point division. fpmacc - floating-point multiply & accumulate. put_vector - vector table modification. pre-programmed motor control functions: 3-phase to 2-phase transformation. 2-phase to 3-phase transformation. forward vector rotation. reverse vector rotation. industrial temperature range -40 c to +85 c operating voltage 5.0 v 5 % package: 144-pin tqfp
a a admc401 - p reliminary t echnical i nformation a analog devices inc., proprietary & confidential 6/5/98 rev 2.1 - information subject to change page 3 of 74 a 14 -a 0 16-bit pwm generation 2 channel auxiliary pwm data address generators adsp-2100 base architecture program sequencer pm address bus dm address bus pm data bus dm data bus dag1 dag2 arithmetic units alu mac shifter interval timer 8-channel, 12-bit adc prog. interrupt controller digital i/o encoder interface event capture timers watchdog timer pm rom 2k x 24 dm ram 1k x 16 pm ram 2k x 24 memory serial ports sport0 sport1 4 2 12 2 8 6 motor control peripherals 6 5 m u x d 23 -d 0 control lines precision 2.5 v reference por figure 1 : functional block diagram of admc401.
a a admc401 - p reliminary t echnical i nformation a analog devices inc., proprietary & confidential 6/5/98 rev 2.1 - information subject to change page 4 of 74 electrical characteristics (v dd = av dd = 5 v 5 %, gnd = agnd = 0 v, t amb = -40 o c to +85 o c, clkin = 13 mhz, unless otherwise specified) parameter test conditions min max unit v ih hi-level input voltage 1,2 @ v dd = max 2.0 v v il lo-level input voltage 1,2 @ v dd = min 0.8 v v t+ positive-going threshold 3 @ v dd = min tbd v v t- negative-going threshold 3 @ v dd = min 0.8 v d v t hysteresis (v t+ - v t- ) 3 @ v dd = min tbd mv v oh hi-level output voltage 1,4,6 @ v dd = min, i oh = -1.0 ma @ v dd = min, i oh = -0.1ma 2.4 v dd - 0.3 v v v ol lo-level output voltage 1,4,6 @ v dd = min, i ol = 2.0 ma 0.4 v v oh hi-level output voltage 5,6 @ v dd = min, i oh = -10.0 ma 2.4 v v ol lo-level output voltage ,5,6 @ v dd = min, i ol = 10.0 ma 0.4 v i ih hi-level input current 7 @ v dd = max, v in = v dd max 10 m a i ih hi-level input current 8 @ v dd = max, v in = v dd max 100 m a i ih hi-level input current 9 @ v dd = max, v in = v dd max 10 m a i il lo-level input current 7 @ v dd = max, v in = 0v 10 m a i il lo-level input current 8 @ v dd = max, v in = 0v 10 m a i il lo-level input current 9 @ v dd = max, v in = 0v 100 m a i ozh hi-level tristate leakage current 10 @ v dd = max, v in = v dd max 10 m a i ozl lo-level tristate leakage current 10 @ v dd = max, v in = 0v 10 m a i dd digital supply current (idle) 11 @ v dd = max tbd ma i dd digital supply current (dynamic) 12 @ v dd = max tbd ma i dd analog supply current (disabled) 13 @ v dd = max tbd ma i dd analog supply current (adc only) 14 @ v dd = max tbd ma i dd analog current (reference + adc) 15 @ v dd = max tbd ma notes: 1. bidirectional pins : d0-d23, rfs0, rfs1, tfs0, tfs1, sclk0 and sclk1. 2. input only pins : pwmtrip , pwmpol, pwmsr , reset , eia, eib, eizp, etu0, etu1, dr1a, dr1b, dr0, clkin, convst, mmap, bmode, br and pwd . 3. programmable input/output pins (pio0 - pio11) with input hysteresis. 4. output pins : pwmsync, aux0, aux1, clkout, dt0, dt1, bg , bgh , pms , dms , bms , rd , wr , pwdack and a0-a13. 5. output pins : ah, al, bh, bl, ch and cl. 6. although specified for ttl outputs, all admc401 outputs are cmos compatible and will drive to v dd -0.3v and gnd+0.3v assuming no dc loads. 7. input only pins reset , eia, eib, eizp, etu0, etu1, dr1a, dr1b, dr0, clkin, convst, mmap, bmode, br and pwd . 8. input pins with internal pull-down pio0 - pio11 and pwmtrip .
a a admc401 - p reliminary t echnical i nformation a analog devices inc., proprietary & confidential 6/5/98 rev 2.1 - information subject to change page 5 of 74 9. input pins with internal pull-up, pwmpol and pwmsr . 10. tri-statable pins : a0-a13, d0-d23, pms , dms , bms , rd , wr , dt0, dt1, rfs0, rfs1, tfs0, tfs1, sclk0, sclk1. 11. idle refers to the admc401 state of operation during execution of the idle instruction. deasserted pins are driven to v dd or gnd. current reflects device operation with clkout disabled. 12. current reflects device operating with no output loads. 13. current reflects device operating with both adc and voltage reference powered down (adcctrl(4) = 1, adcctrl(3::2) = 0x0). 14. current reflects device operating with adc powered on and voltage reference powered down (adcctrl bit 4 = 1) and adcctrl (3::2) =0x10 15. current reflects device operating with adc and voltage reference powered on (adcctrl bit 4 = 0) and adcctrl (3::2) = 0x10. analog to digital converter (v dd = av dd = 5 v 5 %, gnd = agnd = 0 v, t amb = -40 o c to +85 o c, clkin = 13 mhz, adc clock = 8.66 mhz, v1 to v8 = 4.0 v pp , v ref = 2.5 v, unless otherwise specified) parameter test conditions min typ max unit enob effective number of bits f in = 1.0 khz 12 bits snr signal to noise ratio f in = 1.0 khz 74 db snrd signal to noise and distortion f in = 1.0 khz 70 db thd total harmonic distortion f in = 1.0 khz -80 db ctlk channel-channel crosstalk f in = 1.0 khz on 7 channels, dc on other -80 db cmrr common mode rejection ratio tbd db psrr power supply rejection ratio tbd db f s,max sample frequency tbd khz t conv total conversion time (8 channels) 2.0 m s t skew time skew channel to channel 120 ns dnl differential non-linearity 0.5 lsb inl integral non-linearity 1.0 lsb zero error (@ 25 c) tbd ppm/ c gain error (@ 25 c) tbd ppm/ c vin analog input voltage range 4.0 v pp c in input capacitance 10 pf voltage reference (v dd = av dd = 5 v 5 %, gnd = agnd = 0 v, t amb = -40 o c to +85 o c, clkin = 13 mhz, unless otherwise specified) parameter test conditions min typ max unit v refout internal voltage reference 2.475 2.525 v refout source current -1.0 ma v refin refin voltage reference 2.5 v
a a admc401 - p reliminary t echnical i nformation a analog devices inc., proprietary & confidential 6/5/98 rev 2.1 - information subject to change page 6 of 74 r in reference input reference 5 k w
a a admc401 - p reliminary t echnical i nformation a analog devices inc., proprietary & confidential 6/5/98 rev 2.1 - information subject to change page 7 of 74 pulsewidth modulator (v dd = av dd = 5 v 5 %, gnd = agnd = 0 v, t amb = -40 o c to +85 o c, clkin = 13 mhz, unless otherwise specified) parameter test conditions min typ max unit counter resolution 16 bits edge resolution double update mode 38.5 ns t d programmable dead time 0 78.8 m s dead time increments 77 ns t min programmable minimum pulsewidth 0 39.3 m s minimum pulsewidth increments 38.5 ns f pwm pwm switching frequency 16-bit resolution 198 hz f pwm pwm switching frequency 8-bit resolution 101.4 khz t pwmsync pwmsync pulsewidth 38.5 6114 ns pwmsync pulsewidth increments 38.5 ns f chop gate drive chopping frequency 25.39 6500 khz encoder interface (v dd = av dd = 5 v 5 %, gnd = agnd = 0 v, t amb = -40 o c to +85 o c, clkin = 13 mhz, unless otherwise specified) parameter test conditions min typ max unit encoder loop timer timeout rate eiuscale = 0x00 eiuperiod = 0x0001 38.5 ns encoder loop timer timeout rate eiuscale = 0xff eiuperiod = 0xffff 0.65 s t minenc minimum encoder pulsewidth eiufilter = 0x00 115.5 ns t minenc minimum encoder pulsewidth eiufilter = 0x3f 7.39 m s f encmax maximum encoder rate eiufilter = 0x00 3.25 mhz f encmax maximum encoder rate eiufilter = 0x3f 67 khz auxiliary pwm outputs (v dd = av dd = 5 v 5 %, gnd = agnd = 0 v, t amb = -40 o c to +85 o c, clkin = 13 mhz, unless otherwise specified) parameter test conditions min typ max unit resolution 8 bits f aux switching frequency 50.78 13000 khz
a a admc401 - p reliminary t echnical i nformation a analog devices inc., proprietary & confidential 6/5/98 rev 2.1 - information subject to change page 8 of 74 power on reset (v dd = av dd = 5 v 5 %, gnd = agnd = 0 v, t amb = -40 o c to +85 o c, clkin = 13 mhz, unless otherwise specified) parameter test conditions min typ max unit v th , por power on threshold voltage 3.8 4.0 v v th , rst reset threshold voltage 3.5 3.7 v t rst reset time 5.04 ms admc401 - specifications recommended operating conditions parameter b grade min max unit v dd digital supply voltage av dd analog supply voltage t amb ambient operating temperature 4.75 5.25 4.75 5.25 -40 +85 v v o c absolute maximum ratings * supply voltage ................................ ................................ ... 0.3 v to + 7v input voltage ................................ ........................... -0.3 v to v dd + 0.3v output voltage swing ................................ ............. -0.3 v to v dd + 0.3v operating temperature range (ambient) ......................... -40 c to +85 c storage temperature range ................................ ........... -65 c to +150 c lead temperature (5 sec) ................................ ............................ +280 c * stresses above those listed under absolute maximum ratings may cause permanent damage to the device. these are stresses only, and functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability.
a a admc401 - p reliminary t echnical i nformation a analog devices inc., proprietary & confidential 6/5/98 rev 2.1 - information subject to change page 9 of 74 1. general description the admc401 is single-chip dsp-based controller, suitable for high performance control of ac induction motors (acim), permanent magnet synchronous motors (pmsm), brushless dc motors (bdcm) and switched reluctance (sr) motors in industrial applications. the admc401 integrates a 26 mips, fixed-point dsp core with a complete set of motor control peripherals that permits fast motor control in a highly-integrated environment. the dsp core of the admc401 is the adsp-2171 that is completely code compatible with the adsp-21xx dsp family and combines three-computational units, data address generators and a program sequencer. the computational units comprise an alu, a multiplier/accumulator (mac) and a barrel shifter. the adsp-2171 adds new instructions for bit manipulation, multiplication (x squared), biased rounding and global interrupt masking. in addition, two flexible double- buffered, bi-directional synchronous serial ports are included in the admc401. the admc401 provides 2k x 24-bit program memory ram, 2k x 24-bit program memory rom and 1k x 16-bit data memory ram. the program and data memory ram can be boot loaded through the serial port from either a serial e 2 prom, through a uart connection (either from external host microprocessor or from the motion control debugger) or via a synchronous serial interface from a host microprocessor. the program memory rom includes a monitor that adds software debugging features through the serial port. in addition, a number of pre-programmed mathematical and motor control functions are included in the program memory rom. additionally, the admc401 device adds significant external memory and peripheral expansion capabilities by making available the full address and data bus of the dsp core. this feature permits expansion of both external program and data memory and means that the dsp core can address up to 8 k x 24-bits of external program memory and up to 13 k x 16-bits of external data memory. in addition both internal and external program and data memory ram can be boot loaded across the address and data buses from an external eprom. the motor control peripherals of the admc401 comprise a high-performance 8 channel, 12-bit sampling adc system. in addition, a three-phase, 16-bit, center-based pwm generation unit can be used to produce high-accuracy pwm signals with minimal processor overhead. the admc401 also contains a flexible encoder interface unit for position sensor feedback, two auxiliary pwm outputs, 12 line of digital i/o, a two-channel event capture system, a 16-bit watchdog timer, two 16-bit interval timer (one of which can be linked to the encoder interface unit) and a programmable interrupt controller that manages all peripheral interrupts.
a a admc401 - p reliminary t echnical i nformation a analog devices inc., proprietary & confidential 6/5/98 rev 2.1 - information subject to change page 10 of 74 2. pin list pin group name # of pins type function a 13 - a 0 14 o address lines d 23 - d 0 24 i/o data lines pms dms bms , , 3 o external memory select lines rd wr , 2 o external memory read/write enable mmap 1 i memory map select por 1 o internal power on reset output reset 1 i processor reset input. clkout 1 o processor clock output clkin, xtal 2 i external clock or quartz crystal input br 1 i bus request bg 1 o bus grant bgh 1 o bus hang control bmode 1 i boot mode select pwd 1 i powerdown pin pwdack 1 o powerdown acknowledge sport0 5 i/o serial port 0 pins (tfs0, rfs0, dt0, dr0, sclk0) sport1 6 i/o serial port 1 (tfs1/ irq1 , rfs1/ irq0 / srom , dt1/fo, dr1a/fi, dr1b/fi, sclk1) vin1 - vin8 8 i analog inputs vina 1 i analog input to sample & hold amplifier amuxout 1 o analog output of multiplexer vref 1 i/o reference input output refcom 1 gnd reference common cml 1 o common mode level (mid-supply) capt,capb 2 noise reduction pins convst 1 i external convert start ah-cl 6 o pwm outputs pwmtrip 1 i pwm trip signals pwmpol 1 i pwm polarity pin pwmsync 1 o pwm synchronization pin pwmsr 1 i pwm switched reluctance mode control pio0-pio11 12 i/o digital i/o port etu0, etu1 2 i event timer inputs aux0-aux1 2 o auxiliary pwm outputs eia,eib,eizp, eis 4 i encoder interface pins and external eiu latch triggers avdd 2 sup analog power supply agnd 2 gnd analog ground vdd 7 sup digital power supply gnd 19 gnd digital ground table 1 : pin list of admc401 device
a a admc401 - p reliminary t echnical i nformation a analog devices inc., proprietary & confidential 6/5/98 rev 2.1 - information subject to change page 11 of 74 3. dsp core architecture 3.1 dsp c ore f eatures & o verview the adsp-2171 flexible architecture and comprehensive instruction set allow the processor to perform multiple operations in parallel. in one processor cycle (38.5 ns with a 13 mhz crystal) the dsp core can: generate the next program address fetch the next instruction perform one or two data moves update one or two data address pointers perform a computational operation this all takes place while the processor continues to: receive and transmit through the serial ports decrement the interval timer generate pwm signals convert the adc input signals operate the encoder interface units operate all other peripherals including the auxiliary pwm & event timer subsystem the processor contains three independent computational units: the arithmetic & logic unit (alu), the multiplier/accumulator (mac) and the shifter. the computational units process 16-bit data directly and have provisions to support multi-precision computations. the alu performs a standard set of arithmetic and logic operations; division primitives are also supported. the mac performs single-cycle multiply, multiply/add, multiply/subtract operations with 40- bits of accumulation. the shifter performs logical and arithmetic shifts, normalization, denormalization, and derive exponent operations. the shifter can be used to implement efficiently numeric format control including floating-point representations. the internal result (r) bus directly connects the computational units so that the output of any unit may be the input of any unit on the next cycle. a powerful program sequencer and two dedicated data address generators ensure efficient delivery of operands to these computational units. the sequencer supports conditional jumps, subroutine calls and returns in a single cycle. with internal loop counters and loop stacks, the admc401 executes looped code with zero overhead; no explicit jump instructions are required to maintain the loop. two data address generators (dags) provide addresses for simultaneous dual operand fetches from data memory and program memory. each dag maintains and updates four address pointers (i registers). whenever the pointer is used to access data (indirect addressing), it is post-modified by the value in one of four modify (m) registers. a length value may be associated with each pointer (l registers) to implement automatic modulo addressing for circular buffers. the circular buffering feature is also used by the serial ports for automatic data transfers to and from on-chip memory. dag1 generates only data memory addresses but provides an optional bit-reversal capability. dag2 may generate either program or data memory addresses, but has no bit-reversal capability. efficient data transfer is achieved with the use of five internal buses: program memory address (pma) bus program memory data (pmd) bus
a a admc401 - p reliminary t echnical i nformation a analog devices inc., proprietary & confidential 6/5/98 rev 2.1 - information subject to change page 12 of 74 data memory address (dma) bus data memory data (dmd) bus result (r) bus program memory can store both instructions and data, permitting the admc401 to fetch two operands in a single cycle, one from internal program memory and one from internal data memory. the admc401 can fetch an operand from on-chip program memory and the next instruction in the same cycle. the admc401 writes data from its 16-bit registers to the 24-bit program memory using the px register to provide the lower eight bits. when it reads data (not instructions) from 24-bit program memory to a 16-bit data register, the lower eight bits are placed in the px register. the admc401 can respond to a number of distinct dsp core and peripheral interrupts. the dsp core interrupts include serial port receive and transmit interrupts, timer interrupts, software interrupts and external interrupts. in addition, there is a master reset signal. the motor control peripherals also produce interrupts to the dsp core. the two serial ports (sports) provide a complete synchronous serial interface with optional companding in hardware and a wide variety of framed and unframed data transmit and receive modes of operation. each sport can generate an internal programmable serial clock or accept an external serial clock. boot loading of both the program and data memory ram of the admc401 can be through the serial port sport1. alternatively the admc401 can be boot loaded from external parallel memory connected to the external address & date buses of the device. a programmable interval counter is also included in the dsp core and can be used to generate periodic interrupts. a 16-bit count register (tcount) is decremented every n processor cycles, where n-1 is a scaling value stored in the 8-bit tscale register. when the value of the counter reaches zero, an interrupt is generated and the count register is reloaded from a 16-bit period register (tperiod). the admc401 instruction set provides flexible data moves and multifunction (one or two data moves with a computation) instructions. each instruction is executed in a single 38.5 ns processor cycle (for a 13 mhz crystal). the admc401 assembly language uses an algebraic syntax for ease of coding and readability. a comprehensive set of development tools support program development. 3.2 s erial p orts the admc401 incorporates two complete synchronous serial ports (sport0 & sport1) for serial communications and multiprocessor communication. the following is a brief list of the capabilities of the admc401 sports. refer to the adsp-2100 family user?s manual for further details. sports are bidirectional and have a separate, double-buffered transmit and receive section. sports can use an external serial clock or generate their own serial clock internally. sports have independent framing for the receive and transmit sections. sections run in a frameless mode or with frame synchronization signals internally or externally generated. frame synchronization signals are active high or inverted, with either of two pulse widths and timings. sports support serial data word lengths from 3 to 16 bits and provide optional a-law and m -law companding according to ccitt recommendation g.711. sport receive and transmit sections can generate unique interrupts on completing a data word transfer. sports can receive and transmit an entire circular buffer of data with only one overhead cycle per data word. an interrupt is generated after a data buffer transfer.
a a admc401 - p reliminary t echnical i nformation a analog devices inc., proprietary & confidential 6/5/98 rev 2.1 - information subject to change page 13 of 74 sport0 has a multichannel interface to selectively receive and transmit a 24 or 32 word, time-division multiplexed, serial bitstream. sport1 can be configured to have two external interrupts ( irq 0 and irq 1 ), and the flag in and flag out signals. the internally generated serial clock may still be used in this configuration. sport1 is the default input for program and data memory boot loading. the rfs1 pin can be configured internally to the admc401 as an srom/e 2 prom reset signal. sport1 has two data receive pins (dr1a and dr1b). the dr1a pin is intended only for synchronous data receive from the external e 2 prom. the dr1b pin can be used as the data receive pin for a general purpose sport after booting or as the data receive pin for other boot load modes or as the uart/debugger interface. the dr1a and dr1b pins are internally multiplexed onto the one data receive pin of the sport. the particular data receive pin selected is determined by bit 4 of the modectrl register. 3.3 i nterrupt o verview the admc401 can respond to different interrupt sources, some of which are internal dsp core interrupts and others from the motor control peripherals. the dsp core interrupts include a: power up (or reset ) interrupt a peripheral (or irq2 ) interrupt a sport0 receive and a sport0 transmit interrupt a sport1 receive (or irq0 ) and a sport1 transmit (or irq1 ) interrupt two software interrupts an interval timer time out interrupt a powerdown interrupt in addition, the motor control peripherals add other interrupts that include: a pwmsync interrupt an adc end of conversion interrupt an encoder loop timer time out interrupt five peripheral input/output (pio) interrupts an event timer interrupt an encoder count error interrupt a pwm trip interrupt the interrupts are internally prioritized and individually maskable. all peripheral interrupts are multiplexed into the dsp core through the peripheral ( irq2 ) interrupt. the programmable interrupt controller (pic) manages the prioritizing, masking and vector addressing of all peripheral interrupts. 3.4 m emory m ap the admc401 has two distinct memory types; program memory and data memory (in addition to external boot memory). in general program memory contains user code and coefficients, while the data memory is used to store variables and data during program execution. both program memory ram and rom is provided internally on the admc401. internal program memory ram is arranged as a 2k x 24-bit block starting at address 0x0000. a 2k x 24-bit block of internal
a a admc401 - p reliminary t echnical i nformation a analog devices inc., proprietary & confidential 6/5/98 rev 2.1 - information subject to change page 14 of 74 program memory rom is located at address 0x0800. the 4k block of program memory address space starting at address 0x1000 is reserved. however, every effort will be made to make as much of this space as possible available as external program memory address space. internal data memory is arranged as a 1k x 16-bit block starting at address 0x3800. the motor control peripherals are memory mapped into a region of the data memory space starting at 0x2000. the complete program and data memory maps are given in table 2 and table 3 respectively. address range function internal 0x0000-0x005f vector table program 0x0060-0x075f user program space memory 0x0760-0x07df reserved by debugger ram (2k) 0x07e0-0x07ff reserved by monitor internal 0x0800-0x0df6 rom monitor program memory 0x0df7-0x0f4c rom utilities rom (2k) 0x0f4d-0x0fff reserved reserved memory space (4k) 0x1000 - 0x1fff reserved (but some may become external program memory space) external program memory (8k) 0x2000 - 0x3fff user program space (external) table 2 : program memory map of admc401. address range function external data memory (8k) 0x0000-0x1fff external user data space memory mapped registers (1k) 0x2000-0x23ff reserved for memory mapped peripheral registers external data memory (5k) 0x2400-0x3800 external user data space internal data 0x3800-0x3b5f internal user data space memory ram (1k) 0x3b60-0x3bff reserved by monitor reserved (1k) 0x3c00-0x3fff dsp memory mapped registers & reserved. table 3 : data memory map of admc401. 3.5 rom c ode the 2k x 24-bit block of program memory rom starting at address 0x800 contains a monitor function that can be used to download and execute user programs via the serial port. in addition, the monitor function supports an interactive mode in which commands are received and processed from a host that is configured as a uart device. an example of such a host is the windows-based motion control debugger that is part of the software development system for the admc401. in the interactive mode, the host can access both the internal dsp & peripheral motor control registers of the admc401, read & write to both program & data memory, implement breakpoints and perform single-step operation as part of the program debugging cycle. in addition to the monitor function, the program memory rom contains a number of useful mathematical
a a admc401 - p reliminary t echnical i nformation a analog devices inc., proprietary & confidential 6/5/98 rev 2.1 - information subject to change page 15 of 74 and motor control utilities that can be called as subroutines from the user code. a list of the functions and the associated program memory address in the rom code is given in table 4 .
a a admc401 - p reliminary t echnical i nformation a analog devices inc., proprietary & confidential 6/5/98 rev 2.1 - information subject to change page 16 of 74 pm address routine description 0x07f1 per_rst peripheral reset 0x0ded umask limits unsigned value to given range 0x0df4 put_vector facilitates user setup of vector table 0x0e06 smask limits signed value to given range 0x0e26 admc_cos cosine function 0x0e2d admc_sin sine function 0x0e43 arctan arctangent function 0x0e65 reciprocal reciprocal (1/x) function 0x0e7b sqrt square root function 0x0eb5 ln natural logarithm function 0x0eb8 log logarithm (base 10) function 0x0ed4 fltone fixed point to floating point conversion 0x0ed9 fixone floating point to fixed point conversion 0x0edd fpa floating point addition 0x0eec fps floating point subtraction 0x0efc fpm floating point multiplication 0x0f05 fpd floating point division 0x0f26 fpmacc floating point multiply & accumulate 0x0f48 park forward & reverse park transformation (vector rotation) 0x0f5c rev_clark reverse clark transformation (2->3 phase transformation) 0x0f72 for_clark forward clark transformation (3->2 phase transformation) 0x0f80 cos64 64 point cosine table 0x0fc0 one_by_x 16 point 1/x table 0x0fd0 sdivqint unsigned single precision division (integer) 0x0fd9 sdivq unsigned single precision division (fractional) table 4 : rom function descriptions 4. system interface 4.1 c lock s ignals the admc401 can be clocked by either a crystal or by a ttl-compatible clock signal. the clkin input cannot be halted, changed during operation or operated below the specified minimum frequency during normal operation. if an external clock is used, it should be a ttl-compatible signal running at half the instruction rate. the signal is connected to the clkin pin of the admc401. in this mode, with an external clock signal, the xtal pin must be left unconnected. the admc401 uses an input clock with a frequency equal to half the instruction rate; a 13 mhz input clock yields a 38.5 ns processor cycle (which is equivalent to 26 mhz). normally instructions are executed in a single processor cycle. all device timing is relative to the internal instruction rate, which is indicated by the clkout signal when enabled. because the admc401 includes an on-chip oscillator circuit, an external crystal may be used instead of a clock source. the crystal should be connected across the clkin and xtal pins. a parallel-resonant, fundamental frequency,
a a admc401 - p reliminary t echnical i nformation a analog devices inc., proprietary & confidential 6/5/98 rev 2.1 - information subject to change page 17 of 74 microprocessor-grade crystal should be used. a clock output signal (clkout) is generated by the processor at the processor?s cycle rate of twice the input frequency. the timing of the clkin and clkout signals for the admc401 are shown in figure 2 . the period of the clkin signal is denoted by t cki and is equal to 76.9 ns for a 13 mhz clkin. the internal delay from rising edge of clkin to rising edge of clkout is t ckoh . the dsp instruction rate is t ck (the period of the clkout signal) which is equal to 38.5 ns for a 13 mhz clkin (corresponding to a 26 mips device). in addition, t c k is the fundamental time increment of the motor control peripherals. therefore, unless otherwise specified, the motor control peripherals are clocked at a rate equal to clkout. clkin clkout t cki t ckoh t ck figure 2 : clock timing signals for admc401. 4.2 r eset and p ower o n reset (por) c ircuit the reset pin initiates a complete hardware reset of the admc401 when pulled low. the reset signal must be asserted when the device is powered up to assure proper initialization. the admc401 contains an integrated power-on reset (por) circuit that provides an output reset signal, por, from the admc401 on power up and if the power supply voltage falls below the threshold level. the admc401 may be reset from an external source using the reset signal or alternatively the internal power on reset circuit may be used by connecting the por pin to the reset pin. during power up the reset line must be activated for long enough to allow the dsp core?s internal clock to stabilize. the power-up sequence is defined as the total time required for the crystal oscillator to stabilize after a valid v dd is applied to the processor and for the internal phase locked loop (pll) to lock onto the specific crystal frequency. a minimum of 2000 t cki cycles will ensure that the pll has locked (this does not include the crystal oscillator start-up time). the operation of the internal power on reset circuit is illustrated in figure 3 . on power up, the circuit maintains the por pin low until it detects that the v dd line has attained the threshold voltage, v th,por , level. the v th value is nominally set at 3.9 v. as soon as the threshold voltage is attained the power on reset circuit enables a 17-bit counter that is clocked at the clkout rate. while the counter is counting the por pin is held low. when the counter overflows, after a time: t 2 t 2 38 ms 1 17 ck 17 = = = - . . 5 10 5 04 9 the por pin is brought high and if the por and reset pins are connected, the device is brought out of reset.
a a admc401 - p reliminary t echnical i nformation a analog devices inc., proprietary & confidential 6/5/98 rev 2.1 - information subject to change page 18 of 74 v th,rst v th,por v th vdd por nominal values: v dd = 5v v th,por = 3.9v v th,rst = 3.6v t1 t1 = 2^17*t ck = 5.04 ms at 26 mhz clkout t1 v th,rst figure 3 : operation of power on reset (por) circuit of admc401. the internal power on reset circuit also acts as a power supply monitor and puts the por pin at a lo level if it detects a voltage less than v th,rst (nominally 3.6 v). the supply voltage must then exceed v th , por to initiate another power on reset sequence. the master reset ( reset = lo) sets all internal stack pointers to the empty stack condition, masks all interrupts, clears the mstat register and performs a full reset of all of the motor control peripherals. following a power-up, it is possible to initiate a dsp core and motor control peripheral reset by simply pulling the reset low. for these resets, there is no need to wait for pll stabilization and the reset signal must meet the minimum pulse width specification, t rsp . to generate the external reset signal, it is recommended to use either an rc circuit with a schmitt trigger or a commercially available reset ic. a full system reset of the admc401 resets the dsp core and all peripherals excluding the watchdog timer. a software controlled full peripheral reset (excluding the watchdog timer) is achieved by toggling the dsp fl2 flag with the following code segment: preset: set fl2; toggle fl2; toggle fl2; rts; this code segment is available as a rom function (per_rst). a full dsp and peripheral reset will occur automatically on a watchdog trip. 4.3 e xternal m emory i nterface the admc401 can address 8k x 24-bits of external program memory (with possible expansion to 10k) and up to 13k x 16- bits of external data memory. the admc401 provides the address on a 14-bit address bus (a 13 - a 0 ). instructions or data are transferred across the 24-bit data bus (d 23 - d 0 ) during program memory accesses. during data memory accesses, data is transferred on the 16 most significant bits (d 23 - d 8 ) of the data bus. for a dual off-chip fetch, the data from program memory is read first, then the data memory data. the program memory select pin, pms , is activated during external program memory accesses and can be used as a chip select signal for the external memory devices. similarly, for external data memory accesses, the dms pin is activated.
a a admc401 - p reliminary t echnical i nformation a analog devices inc., proprietary & confidential 6/5/98 rev 2.1 - information subject to change page 19 of 74 two control lines indicate the direction of the transfer. memory read, rd , is active low signaling a read from external memory and memory write, wr , is active low signaling a write to external memory. typically, the pms line is connected to the ce (chip enable) of the external program memory and the dms line is connected to the ce line of the external data memory. the rd line is connected to the oe (output enable) pin and the wr is connected to the we (write enable) of both memories. on chip accesses (to internal program memory ram and rom) do not drive any of the external signals. the pms , rd and the wr lines remain high (deasserted) and the address and data buses are tri-stated. similarly, internal accesses to data memory (including internal dm ram and peripheral and dsp core memory mapped registers) also do not drive external signals and the dms , rd and the wr lines remain high (deasserted) and the address and data buses are also tri-stated. the program memory interface can generate between 0 and 7 wait states for external memory devices. the program memory wait state field (pwait) in the system control register (bits 0 - 2) sets the number of wait states that are inserted. the wait states for external data memory accesses is defined by the data memory wait state control register. all internal program memory, data memory and peripheral register accesses are zero wait state. external peripherals can also be connected externally and memory mapped to the external memory space of the admc401. the 16 msbs of the external data bus are connected internally to the 16 lsbs of the dmd. therefore, the data lines d 23 - d 8 should be used for 16-bit peripherals. timing for external program and memory read and write operations are identical to those specified for the adsp-2171 operating at 26 mhz clkout. refer to the datasheet for the adsp-2171 for further details. 4.4 b oot l oading 4.4.1 standalone mode (mmap=bmode=1) boot loading of the admc401 may occur in a number of different ways and is determined by the state of both the mmap and bmode pins. if both mmap and bmode are tied to v dd (hi) then the admc401 is placed in the so-called standalone mode and execution starts from internal program memory rom at address 0x0800 following a power on or reset. this starts execution of the internal monitor function that first performs some initialization functions and copies a default interrupt vector table to addresses 0x0000 - 0x005b of program memory ram. the monitor program next clears bit 4 of the modectrl register to connect the dr1a pin to the internal data receive port (dr1) of sport1. in addition, bit 5 of the modectrl register is set. this connects the fl1 port of the dsp core to the rfs1 / srom pin to act as a reset for a serial memory device. the monitor next attempts to boot load from an external srom or e 2 prom on sport1 using the three wire connection of figure 4 . the monitor program first toggles the rfs1 / srom pin of the admc401 to reset the serial memory device with the following code segment: sromreset: set fl1; toggle fl1; toggle fl1; rts; if an srom or e 2 prom is connected to sport1, data is clocked synchronously into the admc401 at a rate of 1 mb/s. both internal and external program and data memory ram can be loaded from the srom/e 2 prom up to the available capacity of the serial memory device. after the complete boot load is complete, program execution begins at address 0x0060. this is where the first instruction of the user code should be placed.
a a admc401 - p reliminary t echnical i nformation a analog devices inc., proprietary & confidential 6/5/98 rev 2.1 - information subject to change page 20 of 74 admc401 xtal clkin 13 mhz dr1a sclk1 rfs1/srom data clk reset serial rom or e 2 prom reset clkout 20 pf 20 pf mmap bmode v dd figure 4 : admc401 basic system configuration in standalone mode. if boot loading from an e 2 prom is unsuccessful, the monitor code reconfigures sport1 as a uart (setting both bits 4 and 5 of the modectrl register) and attempts to receive commands from an external device on this serial port using the dr1b pin. the monitor now waits for two bytes of information. these bytes are received asynchronously so that no clock is needed. the first bytes is the autobaud byte and it is used to calculate the baud rate at which data is being received. this is known as the autobaud feature. the admc401 will automatically lock onto the baud rate of the external device if it is sent a byte of 0x70. the maximum baud rate that the admc401 will lock onto is 300 kb/s for a 26 mhz clkout. the second byte of information received is the header byte that uniquely identifies to the monitor which type of interface it is connected to. there are six different interfaces supported on the admc401. these includes: a uart boot loader such as from a motorola 68hc11 communicating over its serial communications interface (sci) port. following the boot load, execution begins at address 0x060 of internal program memory ram. a synchronous slave boot loader (the clock is external). a synchronous master boot loader (the admc401 provides the clock). a uart debugger interface such as the motion control debugger from analog devices. the monitor then processes commands received from the debugger over the uart interface. a synchronous master debugger interface. a synchronous slave debugger interface. 4.4.2 eprom boot mode (mmap=bmode=0) if both the mmap and bmode pins are tied to gnd, the admc401 operates in the so-called eprom boot mode . in this mode the entire internal program memory, or any portion of it, can be loaded from an external source using a boot sequence over the memory interface. to allow boot loading from inexpensive eprom devices, the processor loads data one byte at a time. the boot sequence can also be initiated after reset by software. boot memory is organized into eight pages, each of which is 8k bytes long. every fourth byte of a page is an empty byte except for the first one, which contains the page length. each set of three bytes between successive empty bytes contains one 24-bit instruction to be loaded into the internal pm ram of the dsp. the page length is read first and then bytes are loaded from the top of the page downwards. this causes shorter booting times for shorter pages. the length of the boot page is given as: page length = (number of 24-bit pm words/8) - 1
a a admc401 - p reliminary t echnical i nformation a analog devices inc., proprietary & confidential 6/5/98 rev 2.1 - information subject to change page 21 of 74 that is a page length of 0 causes the boot address generator to generate byte addresses for 8 words which reside in 32 sequential eprom locations. following a reset, if both mmap and bmode are lo, the boot sequence always boot loads page 0. after reset, boot loading can occur under program control from any one of up to 8 different boot pages. the boot page select field (bpage) in the memory mapped system control register specifies which boot page is to be loaded. to boot from a specific boot page, first set the bpage bits to the desired value and set the boot force bit (bforce) of the system control register to initiate a boot sequence. the admc401 can boot its internal program memory from a single byte-wide cmos eprom such as the 27c64 or the 27c512. a low-cost commodity-grade eprom with an industry-standard access time can be used. the number of wait states for the boot memory access is selected in the bwait field of the system control register. this field can be set to any value from 0 to 7 to set the number of wait states. the default value for the bwait field is 7 so that 7 wait states are inserted into the boot loading sequence. timing of the boot memory access is identical to that of external program memory or external data memory accesses, except that the active strobe is bms rather than pms or dms . to address eight pages of 8k bytes each, 16 address lines are needed. the least significant 14 bits are output on the 14-bit address bus (a 13 to a 0 ) while the most significant two bits are output on the 2 msbs of the data bus (d 23 and d 22 ) during boot memory accesses. the data is read from the middle eight bits of the data bus (d 15 to d 8 ). 4.4.3 external memory mode (bmode=0, mmap=1) in this mode, with bmode tied to gnd and mmap tied to v dd , the admc401 is placed in external memory mode and there is no boot loading. the effect of this mode is that the internal 2k bank of program memory ram is relocated from the bottom of memory (starting at address 0x0000) to the top of the program memory space (at address 0x3800). in this mode, program execution starts at external memory at address 0x0000. 4.4.4 hip booting (bmode=1, mmap=0) this boot mode is not available on the admc401. it corresponds to boot loading over the host interface port (hip) of the adsp-2171 dsp core. since the hip is not available on the admc401, this combination of the bmode and mmap pins is illegal and the operation of the core is undefined in this state. 4.5 b us r equest /g rant the admc401 can relinquish control of its data and address buses to an external device. the external device requests the bus by asserting (low) the bus request signal br . br is an asynchronous input and if the admc401 is not performing an external access, it responds to the active br input in the following processor cycle by: tri-stating the data and address buses and the pms , dms , bms , rd and wr output drivers asserting the bus grant bg signal, and halting program execution (unless go mode is enabled) if go mode is enabled, the admc401 continues to execute instructions from its internal memory. it will not halt program execution until it encounters an instruction that requires an external access. if go mode is not enabled, the admc401
a a admc401 - p reliminary t echnical i nformation a analog devices inc., proprietary & confidential 6/5/98 rev 2.1 - information subject to change page 22 of 74 always halts before granting the bus. the processors internal state is not affected by granting the bus, and the serial ports remain active during a bus grant, whether or not the processor core halts. if the admc401 is performing an external access when the br signal is asserted, it will not grant the buses until the cycle after the access completes. the entire instruction does not need to be completed when the bus is granted. if a single instruction requires two external accesses, the bus will be granted between the two accesses. the second access is performed after br is removed. when the br input is released, the admc401 releases the bg signal, re-enables the output drivers and continues program execution from the point where it stopped. bg is always deasserted in the same cycle that the removal of br is recognized. the bus request feature operates at all times, including when the admc401 is booting and when reset is active. during reset , bg is asserted in the same cycle that br is recognized. during booting, the bus is granted after the completion of loading of the current byte (including any wait states). using the bus request during booting is one way to bring the booting operation under control of a host computer. the admc401 has an additional output, bus grant hung bgh which lets it operate in a multiprocessor system with a minimum number of wasted cycles. the bgh pin asserts when the admc401 is ready to execute an instruction but is stopped because the external bus is granted to another device. the other device can release the bus by deasserting bus request. once the bus is released, the admc401 deasserts bg and bgh and executes the external access. 4.6 p owerdown m odes the admc401 includes a powerdown feature that allows the device to enter a very low power dormant state through hardware or software control. in the powerdown mode: internal clocks are disabled processor registers and memory contents are maintained ability to recover from powerdown in less than 100 clkin cycles ability to disable internal oscillator when using crystal no need to shut down clock for lowest power when using external oscillator interrupt support for housekeeping code before entering powerdown and after recovering from powerdown user selectable power-up context 4.6.1 entering powerdown the powerdown sequence is initiated by applying a high-to-low transition on the pwd pin or by setting the powerdown force control bit (pdforce) of the sport1 autobuffer/powerdown control register. the dsp core then vectors to the non-maskable powerdown interrupt vector at address 0x002c. care must be exercise to ensure that multiple powerdown interrupts do not occur or else stack overflow may result. the interrupt service routine at address 0x002c can be used to execute any number of housekeeping instructions prior to the processor entering the powerdown mode. typically, this is used to configure the powerdown state, disable on-chip peripherals and clear pending interrupts. the dsp subsequently enters the powerdown mode when it executes the idle instruction (while pwd is asserted). the processor may take either one or two cycles to power down depending on internal clock states during execution of the idle instruction. all register and memory contents are maintained in powerdown. also, all active outputs are held in whatever state they are in before going into powerdown. if an rti instruction is executed before the idle instruction, the processor returns from the powerdown interrupt and the powerdown sequence is aborted.
a a admc401 - p reliminary t echnical i nformation a analog devices inc., proprietary & confidential 6/5/98 rev 2.1 - information subject to change page 23 of 74 4.6.2 exiting powerdown the powerdown mode can be exited with the use of the pwd pin or with the reset pin. there are also several user- selectable modes for startup from powerdown which specify a startup delay as well as specify the program flow after startup. this allows the program to resume from where it left off before powerdown or for the program context to be cleared. applying a low-to-high transition on the pwd pin will take the processor out of powerdown. the amount of time it takes for the processor to come out of powerdown is controllable with the delay startup from powerdown control bit (xtaldelay, bit 14 of the powerdown control register). if this bit is cleared, no additional delay over the quick startup (100 cycles) is introduced. if this bit is set, a delay of 4096 cycles is introduced. the context for exiting powerdown is set by bit 12 (pucr) of the powerdown control register. if this bit is cleared, the processor will continue to execute instructions following the idle instruction following the low-to-high transition on the pwd pin. when the rti instruction is encountered in the interrupt service routine for the powerdown, operation is returned to the main routine. if the pucr bit is set for a clear context, the processor resumes operation from powerdown by clearing the pc, status, loop and cntr registers. the imask and astat registers are cleared and the sstat goes to 0x55. the processor starts execution at address 0x0000. active output pins retain their states during powerdown. in addition, interrupts are latched and can be services if the admc401 exits powerdown with pucr = 0. it is possible to clock data into or out of the serial ports during powerdown by supplying an external serial clock. data clocked into the admc401 will remain in the rx registers. these activities cause additional power consumption. if reset is activated while the admc401 is in the powerdown mode, the device is reset and instructions are executed and the device is boot loaded according to the settings of mmap and bmode pins. when exiting powerdown with reset , the xtaldelay control bit is ignored. 4.6.3 startup time after powerdown the time required to exit the powerdown state depends on whether an internal or external oscillator is used, and the method used to exit powerdown. when the admc401 is in powerdown, the external clock signal (assuming the device is driven by an external ttl/cmos clock) is ignored if the xtaldis bit (bit 15 of the powerdown control register) is set. it is therefore not necessary to stop the external clock since no power is wasted while this external clock is running. after the processor comes out of powerdown by either the pwd or reset pins, it will begin executing after a maximum startup time of 100 clkin cycles as long as the clock oscillator is stable and at the same frequency as before powerdown. if the external clock is unstable when the admc401 exits powerdown, then the xtaldelay control bit can be used to insert an additional 4096 cycle delay into the startup time. this delay can only be inserted when the admc401 is brought out of powerdown by the pwd pin. if the processor is taken out of powerdown by the reset line and the clock is stable and at the same frequency as before powerdown, the reset need only be held for 5 cycles. if using an external crystal and the internal oscillator of the admc401, the startup sequence is somewhat different in that a trade-off must be made between a fast startup time and minimal power consumption during powerdown. if a fast startup is desired, then both the xtaldelay and xtaldis bits must be cleared so that the oscillator will continue to operate (and consume power) during powerdown and no startup delay time is inserted. in this configuration, the admc401 will begin execution at least 100 clkin cycles after the low-to-high transition at the pwd pin. if lowest possible power consumption possible is required, then both the xtaldelay and xtaldis bits must be set before entering powerdown (with the idle instruction). if the reset line is used to exit powerdown and the clock has been stopped (xtaldis is set), then the
a a admc401 - p reliminary t echnical i nformation a analog devices inc., proprietary & confidential 6/5/98 rev 2.1 - information subject to change page 24 of 74 reset line must be held low for 1000 clkin cycles plus the time required for the pll to lock and the crystal oscillator to stabilize (2000 clkin cycles). if the clock is running during powerdown, the reset need only be asserted for 5 cycles. 4.6.4 the pwdack pin the pwdack pin is an output that indicates when the admc401 is in the powerdown mode. this pin is driven high by the processor when it has powered down. it is driven low after the processor has completed the power-up sequence. a low level on the pwdack pin also indicates that there is a valid clkout signal and that instruction execution has begun. 4.6.5 using powerdown as a non-maskable interrupt the powerdown interrupt is never masked. it is possible to use this interrupt for other purposes, if desired. the admc401 does not go into powerdown until the idle instruction is executed. if an rti is executed instead the processor returns from the powerdown interrupt routine and the powerdown sequence is aborted. 5.0 the analog to digital conversion system 5.1 o verview the admc401 contains a fast, high-accuracy, multiple-input analog to digital conversion system that is needed for accurate measurement of currents, voltages and other signals in high performance motor control systems. a functional block diagram of the entire adc system is shown in figure 5 . the adc system consists of an 8-to-1 line multiplexer, a sample and hold amplifier and a 12-bit pipeline flash analog to digital converter. up to eight analog inputs may be applied at the pins vin1 to vin8. the output of the internal analog multiplexer is available at the amuxout pin. it is necessary to connect a high quality unity gain non-inverting amplifier between the amuxout and vina pins to provide sufficient drive to the sample and hold amplifier. in normal operation, the adc system converts the eight analog input signals sequentially on receipt of a convert start command. the convert start trigger may be internally or externally generated. as the conversion for a given analog input channel is completed, the corresponding digital number is written to a dedicated 16-bit, 2?s complement, left-aligned register that is memory mapped to the data memory space of the dsp core. the adc may use either an internally generated 2.5 v reference voltage or an externally supplied reference voltage level at the vref pin. when selected, the internally generated reference voltage is also made available at the vref pin for use by external circuitry. operation of the adc system is controlled by the adcctrl register. another register, adctest, may be used to enable a manual channel select feature that permits a single channel only to be selected for conversion on the occurrence of a convert start command. 5.2 c onvert s tart c ommand the analog to digital conversion process (consisting of the sequential conversion of all eight analog inputs or the channel selected in the adctest register) of the admc401 may be started by either an internal or an external command. bit 0 of the adcctrl register determines whether internal or external convert start mode is enabled. if bit 0 of the adcctrl register is cleared, internal convert start mode is selected and the adc conversion process is started on the rising edge of the pwmsync signal. therefore, in this internal convert start mode, there is one conversion process per pwm period when the single update mode is enabled in the pwm subsystem. in double update pwm mode, there are two complete conversion processes per pwm period. if bit 0 of the adcctrl register is set, external convert start mode is selected. in this mode, the conversion process is started on the occurrence of a rising edge on the convst pin. the start of conversion could be placed under software control by connecting one of the programmable input/output lines to the convst pin and generating a rising edge by
a a admc401 - p reliminary t echnical i nformation a analog devices inc., proprietary & confidential 6/5/98 rev 2.1 - information subject to change page 25 of 74 writing to the piodata register. by default, following a power on or reset, bit 0 of the adcctrl register is cleared so that internal convert start mode is selected. 5.3 adc c hannel s elect , adctest r egister the adctest register can be used to overwrite the normal sequential conversion process of the adc. instead a single channel can be selected by programming the address into adctest(2::0). for example, writing adctest(2::0) = 0x00 selects analog input vin1 for conversion, adctest(2::0) = 0x001 selects analog input vin2 etc. bit 3 of the adctest register controls the mode of the conversion. if adctest(3) is set, the single channel convert mode is selected and the channel to be converted is read from adctest(2::0). if adctest(3) is cleared the normal sequence of eight channels converted is selected. the default value is that adctest(3) is cleared to select the eight channel sequence mode. adc1(15:0) adc2(15:0) adc3(15:0) adc4(15:0) adc5(15:0) adc6(15:0) adc7(15:0) adc8(15:0) 12-bit pipeline flash adc vin1 vin2 vin3 vin4 vin5 vin6 vin7 vin8 8 to 1 mux s&h adcctrl(1:0) adc control convst pwmsync 2.5v +/- 1 % reference vref vina amuxout adcctrl(3:2) clock divide clkout adc clock adctest(3:0) refcom cml, capt, capb figure 5 : functional block diagram of the adc system of the admc401. 5.4 adc t iming and c lock s ignals the adc consists of a three stage pipeline flash architecture and is clocked at an integer fraction of the dsp instruction rate. all of the timing of the adc system is regulated by this clock signal and it determines the total conversion time as well as the skew between sampling of successive input channels. the adc clock rate is controlled by bits 2 and 3 of the adcctrl register. the period of the adc clock, t ck,adc is related to the dsp clkout period by: ( ) t n 1 t ck, adc ck = +
a a admc401 - p reliminary t echnical i nformation a analog devices inc., proprietary & confidential 6/5/98 rev 2.1 - information subject to change page 26 of 74 where n is the 2 bit value written to adcctrl(3::2). clearing both bits 2 and 3 of the adcctrl register disables the adc clock signal, effectively powering down the adc system. by default, following a power on or reset, bit 2 of the adcctrl register is cleared and bit 3 is set so that the adc clock frequency is a third of the clkout rate (or 8.67 mhz for a 26 mhz clkout). this corresponds to a t ck , adc of approximately 115 ns. the timing of the adc conversion process is shown in figure 6 where the convert start command may be derived either internally or externally, as described previously. at the rising edge of the convert start signal, the analog voltage on the vin1 pin is automatically fed through the multiplexer and sampled by the sample and hold amplifier. it takes one adc clock cycle to successfully select an analog input channel and lock onto it with the sample & hold amplifier. it takes a further three and a half clock cycles to complete the conversion of the sampled voltage. therefore, four and a half clock cycles (4.5t ck , adc ) after the sample instant the digital output word is latched to the corresponding adc1 register. however, because of the pipeline nature of the adc, it is possible to sample the second analog input, vin2, after only one clock cycle. therefore the time skew between samples of successive analog inputs is only one clock period, t ck , adc . therefore, in the second clock period, the sampled v 2 goes through the first stage of the adc pipeline while the sample of vin3 goes through the second stage. adc clock t ck,adc 3.5t ck,adc convert start adc1 adc2 adc3 sample vin1 sample vin2 sample vin3 latch adc1 latch adc3 latch adc8 : : adc8 sample vin8 adc interrupt t conv adcstat bit 0 start conversion of vin1 end conversion of vin1 3.5t ck,adc start conversion of vin2 end conversion of vin2 latch adc2 figure 6 : representation of timing of adc conversion process. clearly, this pipelined sampling and conversion process continues until all eight channels have been sequentially sampled, converted and the corresponding digital word written to the appropriate register. the input channels are always converted in
a a admc401 - p reliminary t echnical i nformation a analog devices inc., proprietary & confidential 6/5/98 rev 2.1 - information subject to change page 27 of 74 the same order and all channels are converted at each convert start trigger. as a result, it can be seen that the entire conversion time for the eight channels is equal to seven time skews plus the time required to convert the final channel or: t 7 t 4.5 t 11.5 t conv skew ck, adc ck, adc = + = so that with an 8.67 mhz adc clock rate (default value at 26 mhz clkout) the eight analog inputs are converted in slightly more than 1.32 m s. any additional delays in latching the data into the appropriate registers and performing any other tasks must be such that at most 2 m s after the convert start signal, all data in the registers adc1 to adc8 is valid. 5.5 adc s tatus and i nterrupts at the end of the conversion process as illustrated in figure 6 , an adc interrupt is generated that is applied to the peripheral interrupt controller (pic) block. this interrupt signals that the conversion of all eight channels has been completed and that the data in the eight adc registers (adc1 to adc8) is now valid. this interrupt can be masked by the picmask register as part of the pic control and operation. a one bit read only adcstat register is used to give the operational status of the adc. while the adc is converting this status bit is set. reading this register does not alter the contents of the register. this register can be used in a polling routine to wait until the end of conversion. following the completion of the conversion process and the generation of the adc interrupt, this status bit is cleared, automatically. it is possible (particularly when using external convert start mode) that a second convert start trigger may be applied while the adc is still converting. in this case, the present conversion process continues as normal and the additional convert start signal is ignored. therefore, the onus is on the user of the adc block to ensure that multiple external convert start signal not be applied to the device as otherwise convert start triggers will be missed. 5.6 v oltage r eferences the admc401 contains an internal 2.5v 1% voltage reference that may be used by the adc to eliminate the need for an external voltage reference. the output of this voltage reference is made available at the vref pin when internal reference is selected and can be used by external biasing and scaling circuitry, if required. to prevent excessive loading of this internal reference, it should be buffered in a suitable unity gain, non-inverting stage prior to use by external circuitry. the internal voltage reference is selected by clearing bit 1 of the adcctrl register. alternatively, if the required accuracy or thermal drift characteristics of the application require a more accurate reference, it may be connected at the vref pin. use of this external voltage reference for the adc conversion is selected by setting bit 1 of the adcctrl register. the default condition following power up or reset is that bit 1 of the adcctrl register is cleared and the internal voltage reference is selected. 5.7 adc t ransfer c haracteristics the analog input voltages on input pins have a nominal input voltage range of 4.0 v pp . in normal operation a 2.5v reference voltage is used and the input voltages may be in the range 0.5v to 4.5v. consequently, the transfer characteristics of each of the adc channels may be written: adcn = 0x7ff0 vinn 4.5v 0x0000 vinn 2.5v 0x8000 vinn 0.5v if if if = = = ? ? ?
a a admc401 - p reliminary t echnical i nformation a analog devices inc., proprietary & confidential 6/5/98 rev 2.1 - information subject to change page 28 of 74 where n (1 to 8) is the channel number. therefore, the 12-bit data from the adc is stored in 2?s complement, left-aligned form in the 16-bit data registers. in normal operation (analog input voltage is in range), the least four significant bits of adc1 to adc8 are always cleared. the adc also provides an out of range detector that is set when the input signal of a given channel exceeds the allowable input voltage range. when this condition is detected for a given analog input, the least significant bit (bit 0) of the corresponding register is set. consequently, the condition of the analog input signal for a given channel may be established by examination of both the msb and lsb of the associated adc data register, according to table 5 . msb lsb input voltage is 0 0 in range, 2.5 v vin n 4.5 v 1 0 in range, 0.5 v vin n < 2.5 v 0 1 over range, vin n > 4.5 v 1 0 under range, vin n < 0.5 v table 5 : out of range indication for analog input voltages. 5.8 adc r egisters the structure of the adc registers is described in figure 7 .
a a admc401 - p reliminary t echnical i nformation a analog devices inc., proprietary & confidential 6/5/98 rev 2.1 - information subject to change page 29 of 74 adc1 (r) adc2 (r) adc3 (r) adc4 (r) adc5 (r) adc6 (r) adc7 (r) adc8 (r) dm (0x2030) dm (0x2031) dm (0x2032) dm (0x2033) dm (0x2034) dm (0x2035) dm (0x2036) dm (0x2037) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 adcctrl (r/w) dm (0x2038) 1 0 0 0 convert start 1=external (convst) 0=internal (pwmsync) voltage reference 1=external 0=internal adc clock control 00 = disable 01 = clkout/2 10 = clkout/3 11 = clkout/4 0 0 0 adc data adc out of rangebit 1=out of range 0=in range 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 adcstat (r) dm (0x2039) adc status 1=busy (converting) 0=finished 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 adctest (r/w) dm (0x203a) adc channel select 000 = vin1 001 = vin2 010 = vin3 011 = vin4 100 = vin5 101 = vin6 110 = vin7 111 = vin8 adc mode 1=single channel 0=eight channel sequence 0 0 0 0 figure 7 : structure of adc registers of admc401 (shaded bits are unused, reset values included, where defined).
a a admc401 - p reliminary t echnical i nformation a analog devices inc., proprietary & confidential 6/5/98 rev 2.1 - information subject to change page 30 of 74 6. the pwm controller. 6. 1 o verview the pwm generator block of the admc401 is a flexible, programmable, three-phase pwm waveform generator that can be programmed to generate the required switching patterns to drive a three-phase voltage source inverter for ac induction (acim) or permanent magnet synchronous (pmsm) motor control. in addition, the pwm block contains special functions that considerably simplify the generation of the required pwm switching patterns for control of the electronically commutated motor (ecm) or brushless dc motor (bdcm). a special mode for switched reluctance motors (srm) is enabled by tying a dedicated pin, pwmsr to gnd. the pwm generator produces three pairs of pwm signals on the six pwm output pins (ah, al, bh, bl, ch and cl). the six pwm output signals consist of three high-side drive signals (ah, bh and ch) and three low-side drive signals (al, bl and cl). the polarity of the generated pwm signals may be programmed by the pwmpol pin, so that either active hi or active lo pwm patterns can be produced by the admc401. the switching frequency, dead time and minimum pulse widths of the generated pwm patterns are programmable using respectively the pwmtm, pwmdt and pwmpd registers. in addition, three duty-cycle control registers (pwmcha, pwmchb and pwmchc) directly control the duty cycles of the three-pairs of pwm signals. each of the six pwm output signals can be enabled or disabled by separate output enable bits of the pwmseg register. in addition, three control bits of the pwmseg register permit crossover of the two signals of a pwm pair for easy control of ecm or bdcm. in crossover mode, the pwm signal destined for the high-side switch is diverted to the complementary low-side output and the signal destined for the low-side switch is diverted to the corresponding high-side output signal. in addition to ease of use of the pwm controller for ecm or bdcm, this crossover mode can also be used to transition the pwm signals into the over-modulation range with relative ease. in many applications, there is a need to provide an isolation barrier in the gate-drive circuits that turn on the power devices of the inverter. in general, there are two common isolation techniques, optical isolation using opto-couplers and transformer isolation using pulse transformers. the pwm controller of the admc401 permits mixing of the output pwm signals with a high-frequency chopping signal to permit easy interface to such pulse transformers. the features of this gate-drive chopping mode can be controlled by the pwmgate register. there is an 8-bit value within the pwmgate register that directly controls the chopping frequency. in addition, high-frequency chopping can be independently enabled for the high- side and the low-side outputs using separate control bits in the pwmgate register. the pwm generator is capable of operating in two distinct modes, single update mode or double update mode. in single update mode the duty cycle values are programmable only once per pwm period, so that the resultant pwm patterns are symmetrical about the mid-point of the pwm period. in the double update mode, a second updating of the pwm registers is implemented at the mid-point of the pwm period. in this mode, it is possible to produce asymmetrical pwm patterns, that produce lower harmonic distortion in three-phase pwm inverters. this technique also permits closed loop controllers to change the average voltage applied to the machine windings at a faster rate and so permits faster closed loop bandwidths to be achieved. the operating mode of the pwm block (single or double update mode) is selected by a control bit in modectrl register. the pwm generator of the admc401 also provides an output pulse on the pwmsync pin that is synchronized to the pwm switching frequency. in single update mode a pwmsync pulse is produced at the start of each pwm period. in double update mode, an additional pwmsync pulse is produced at the mid-point of each pwm period. the width of the pwmsync pulse is programmable through the pwmsyncwt register.
a a admc401 - p reliminary t echnical i nformation a analog devices inc., proprietary & confidential 6/5/98 rev 2.1 - information subject to change page 31 of 74 the pwm signals produced by the admc401 can be shut-off in a number of different ways. firstly, there is a dedicated asynchronous pwm shutdown pin, pwmtrip , that, when brought lo, instantaneously places all six pwm outputs in the off state (as determined by the state of the pwmpol pin). in addition, each of the pio lines of the admc401 (pio0 to pio11) can be configured to act as an additional pwm shutdown. by setting the appropriate bit in the piopwm register, the corresponding pio line acts as an asynchronous pwm shutdown source in a manner identical to the pwmtrip pin. these two hardware shutdown mechanisms are asynchronous so that the associated pwm disable circuitry does not go through any clocked logic, thereby ensuring correct pwm shutdown even in the event of a loss of the dsp clock. in addition to the hardware shutdown features, the pwm system may be shutdown in software by writing to the pwmswt register. status information about the pwm system of the admc401 is available to the user in the sysstat register. in particular, the state of the pwmtrip and pwmpol pins is available, as well as status bits that indicates whether operation is in the first half or the second half of the pwm period and whether switched reluctance mode is enabled or disabled. a functional block diagram of the pwm controller is shown in figure 8 . the generation of the six output pwm signals on pins ah to cl is controlled by four important blocks: the three-phase pwm timing unit, which is the core of the pwm controller, generates three pairs of complemented and dead time adjusted center based pwm signals. the output control unit allows the redirection of the outputs of the three-phase timing unit for each channel to either the high-side or the low-side output. in addition, the output control unit allows individual enabling/disabling of each of the six pwm output signals. the gate drive unit provides the correct polarity output pwm signals based on the state of the pwmpol pin. the gate drive unit also permits the generation of the high-frequency chopping frequency and its subsequent mixing with the pwm signals. the pwm shutdown controller takes care of the various pwm shutdown modes (via the pwmtrip pin, the pio lines or the pwmswt register) and generates the correct reset signal for the timing unit. the pwm controller is driven by a clock at the same frequency as the dsp instruction rate, clkout and is capable of generating two interrupts to the dsp core. one interrupt is generated on the occurrence of rising edge on the pwmsync pulse and the other is generated on the occurrence of any pwm shutdown action. 6. 2 t hree -p hase t iming u nit the 16-bit three-phase timing unit is the core of the pwm controller and produces three pairs of pulsewidth modulated signals with high resolution and minimal processor overhead. the outputs of this timing unit are active lo such that a low level is interpreted as a command to turn on the associated power device. there are four main configuration registers (pwmtm, pwmdt, pwmpd and pwmsyncwt) that determine the fundamental characteristics of the pwm outputs. in addition, the operating mode of the pwm (single or double update mode) is selected by bit 6 of the modectrl register. these registers in conjunction with the three 16-bit duty cycle registers (pwmcha, pwmchb and pwmchc) control the output of the three-phase timing unit.
a a admc401 - p reliminary t echnical i nformation a analog devices inc., proprietary & confidential 6/5/98 rev 2.1 - information subject to change page 32 of 74 pwmtm (0-15) pwmdt (0-9) pwmpd (0-9) pwmsyncwt (0-7) modectrl(6) pwmcha (0-15) pwmchb (0-15) pwmchc (0-15) three-phase pwm timing unit clk sync sr reset output control unit pwmseg (0-8) gate drive unit pwmgate (0-9) ah al bh bl ch cl sync clk pol clkout pwmsync pwmpol pwmtrip pio pwm detect : : pio0 pio11 piopwm (0-11) pwmswt (0) or to interrupt controller pwm shutdown controller pwm configuration registers pwm duty cycle registers pwmtrip pwmsync pwmsr figure 8 : overview of the pwm controller of the admc401. 6.2.1 pwm switching frequency, pwmtm register the pwm switching frequency is controlled by the 16-bit read/write pwm period register, pwmtm. the fundamental timing unit of the pwm controller is t ck (dsp instruction rate). therefore, for a 26 mhz clkout, the fundamental time increment is 38.5 ns. the value written to the pwmtm register is effectively the number of t ck clock increments in half a pwm period. the required pwmtm value as a function of the desired pwm switching frequency (f pwm ) is given by: pwmtm f 2 f f f clkout pwm clkin pwm = = therefore, the pwm switching period, t s , can be written as: t 2 pwmtm t s ck = for example, for a 26 mhz clkout and a desired pwm switching frequency of 10 khz (t s = 100 m s), the correct value to load into the pwmtm register is:
a a admc401 - p reliminary t echnical i nformation a analog devices inc., proprietary & confidential 6/5/98 rev 2.1 - information subject to change page 33 of 74 pwmtm 26 10 2 10 10 1300 6 3 = = the largest value that can be written to the 16-bit pwmtm register is 0xffff = 65,535 which corresponds to a minimum pwm switching frequency of: f 26 10 2 65,535 198 hz pwm, min 6 = = 6.2.2 pwm switching dead time, pwmdt register the second important parameter that must be set up in the initial configuration of the pwm block is the switching dead time. this is a short delay time introduced between turning off one pwm signal (say ah) and turning on the complementary signal, al. this short time delay is introduced to permit the power switch being turned off (ah in this case) to completely recover its blocking capability before the complementary switch is turned on. this time delay prevents a potentially destructive short-circuit condition from developing across the dc link capacitor of a typical voltage source inverter. the dead time is controlled by the 10-bit, read/write pwmdt register. there is only one dead time register that controls the dead time inserted into the three pairs of pwm output signals. the dead time, t d , is related to the value in the pwmdt register by: t pwmdt 2 t d ck = therefore, a pwmdt value of 0x00a (= 10), introduces a 770 ns delay between the turn off on any pwm signal (say ah) and the turn on of its complementary signal (al). the amount of the dead time can therefore be programmed in increments of 2t ck (or 77 ns for a 26 mhz clkout). the pwmdt register is a 10-bit register so that its maximum value is 0x3ff (= 1023) corresponding to a maximum programmed dead time of: t 1023 2 t 1023 2 38.5 10 78.77 s d, max ck 9 = = = - m for a clkout rate of 26 mhz. obviously, the dead time can be programmed to be zero by writing 0 to the pwmdt register. 6.2.3 pwm operating mode, modectrl & sysstat registers the pwm controller of the admc401 can operate in two distinct modes; single update mode and double update mode. the operating mode of the pwm controller is determined by the state of bit 6 of the modectrl register. if this bit is cleared the pwm operates in the single update mode. setting bit 6 places the pwm in the double update mode. by default, following either a peripheral reset or power on, bit 6 of the modectrl register is cleared so that the default operating mode is single update mode. in single update mode, a single pwmsync pulse is produced in each pwm period. the rising edge of this signal marks the start of a new pwm cycle and is used to latch new values from the pwm configuration registers (pwmtm, pwmdt, pwmpd and pwmsyncwt) and the pwm duty cycle registers (pwmcha, pwmchb and pwmchc) into the three- phase timing unit. in addition, the pwmseg register is also latched into the output control unit on the rising edge of the pwmsync pulse. in effect, this means that the characteristics and resultant duty cycles of the pwm signals can be
a a admc401 - p reliminary t echnical i nformation a analog devices inc., proprietary & confidential 6/5/98 rev 2.1 - information subject to change page 34 of 74 updated only once per pwm period at the start of each cycle. the result is that pwm patterns that are symmetrical about the mid-point of the switching period are produced. in double update mode, there is an additional pwmsync pulse produced at the mid-point of each pwm period. the rising edge of this new pwmsync pulse is again used to latch new values of the pwm configuration registers, duty cycle registers and the pwmseg register. as a result it is possible to alter both the characteristics (switching frequency, dead time, minimum pulse width and pwmsync pulsewidth) as well as the output duty cycles at the mid-point of each pwm cycle. consequently, it is possible to produce pwm switching patterns that are no longer symmetrical about the mid-point of the period (asymmetrical pwm patterns). in the double update mode, it may be necessary to know whether operation at any point in time is in either the first half or the second half of the pwm cycle. this information is provided by bit 3 of the sysstat register which is cleared during operation in the first half of each pwm period (between the rising edge of the original pwmsync pulse and the rising edge of the new pwmsync pulse introduced in double update mode). bit 3 of the sysstat register is set during operation in the second half of each pwm period. this status bit allows the user to make a determination of the particular half-cycle during implementation of the pwmsync interrupt service routine, if required. the advantage of the double update mode is that lower harmonic voltages can be produced by the pwm process and faster control bandwidths are possible. however, for a given pwm switching frequency, the pwmsync pulses occur at twice the rate in the double update mode. since, new duty cycle values must be computed in each pwmsync interrupt service routine, there is a larger computational burden on the dsp in the double update mode. alternatively, the same pwm update rate may be maintained at half the switching frequency to give lower switching losses. 6.2.4 width of the pwmsync pulse, pwmsyncwt register. the pwm controller of the admc401 produces an output pwm synchronization pulse at a rate equal to the pwm switching frequency in single update mode and at twice the pwm frequency in the double update mode. this pulse is available for external use at the pwmsync pin. the width of this pwmsync pulse is programmable by the 8-bit read/write pwmsyncwt register. the width of the pwmsync pulse, t pwmsync , is given by: ( ) t t pwmsyncwt 1 pwmsync ck = + so that the width of the pulse is programmable from t ck to 256t ck (corresponding to 38.5 ns to 9.856 m s for a clkout rate of 26 mhz). following a reset, the pwmsyncwt register contains 0x27 ( = 39) so that the default pwmsync width is 1.54 m s, again for a 26 mhz clkout. 6.2.5 pwm duty cycles, pwmcha, pwmchb, pwmchc registers the duty cycles of the six pwm output signals on pins ah to cl are controlled by the three 16-bit read/write duty cycle registers, pwmcha, pwmchb and pwmchc. the integer value in the register pwmcha controls the duty cycle of the signals on ah and al, in pwmchb control the duty cycle of the signals on bh and bl and in pwmchc controls the duty cycle of the signals on ch and cl. the duty cycle registers are programmed in integer counts of the fundamental time unit, t ck , and define the desired on-time of the high-side pwm signal produced by the three-phase timing unit over half the pwm period. the switching signals produced by the three-phase timing unit are also adjusted to incorporated the programmed dead time value in the pwmdt register. the three-phase timing unit produces active lo signals so that a lo level corresponds to a command to turn on the associated power device.
a a admc401 - p reliminary t echnical i nformation a analog devices inc., proprietary & confidential 6/5/98 rev 2.1 - information subject to change page 35 of 74 a typical pair of pwm outputs (in this case for ah and al) from the timing unit are shown in figure 9 for operation in single update mode. all illustrated time values indicate the integer value in the associated register and can be converted to time by simply multiplying by the fundamental time increment, t ck . firstly, it is noted that the switching patterns are perfectly symmetrical about the mid-point of the switching period in this single update mode since the same values of pwmcha, pwmtm and pwmdt are used to define the signals in both half cycles of the period. it can be seen how the programmed duty cycles are adjusted to incorporate the desired dead time into the resultant pair of pwm signals. clearly, the dead time is incorporated by moving the switching instants of both pwm signals (ah & al) away from the instant set by the pwmcha register. both switching edges are moved by an equal amount (pwmdt*t ck ) to preserve the symmetrical output patterns. also shown is the pwmsync pulse whose width is set by the pwmsyncwt register and bit 3 of the sysstat register that indicates whether operation is in the first or second half cycle of the pwm period. pwmtm pwmtm pwmcha pwmcha 2*pwmdt 2*pwmdt ah al pwmsync sysstat (3) pwmsyncwt + 1 figure 9 : typical pwm outputs of three-phase timing unit in single update mode (active lo waveforms). the resultant on-times of the pwm signals over the full pwm period (two half periods) produced by the pwm timing unit and illustrated in figure 9 may be written as: ( ) ( ) t 2 pwmcha pwmdt t t 2 pwmtm - pwmcha pwmdt t ah ck al ck = - = - and the corresponding duty cycles are: d t ts pwmcha pwmdt pwmtm d t ts pwmtm - pwmcha pwmdt pwmtm ah ah al al = = - = = - obviously negative values of t ah and t al are not permitted and the minimum permissible value is zero, corresponding to a 0% duty cycle. in a similar fashion, the maximum value is t s , corresponding to a 100% duty cycle.
a a admc401 - p reliminary t echnical i nformation a analog devices inc., proprietary & confidential 6/5/98 rev 2.1 - information subject to change page 36 of 74 the output signals from the timing unit for operation in double update mode are shown in figure 10 . this illustrates a completely general case where the switching frequency, dead time and duty cycle are all changed in the second half of the pwm period. of course, the same value for any or all of these quantities could be used in both halves of the pwm cycle. however, it can be seen that there is no guarantee that symmetrical pwm signal will be produced by the timing unit in this double update mode. additionally, it is seen that the dead time is inserted into the pwm signals in the same way as in the single update mode. pwmtm 1 pwmtm 2 pwmcha 1 pwmcha 2 2*pwmdt 2 2*pwmdt 1 ah al pwmsync sysstat (3) pwmsyncwt 2 + 1 pwmsyncwt 1 + 1 figure 10 : typical pwm outputs of three-phase timing unit in double update mode (active lo waveforms). in general the on-times of the pwm signals over the full pwm period in double update mode can be defined as: ( ) ( ) t pwmcha pwmcha pwmdt pwmdt t t pwmtm pwmtm pwmcha pwmcha pwmdt pwmdt t ah 1 2 1 2 ck al 1 2 1 2 1 2 ck = + - - = + - - - - where the subscript 1 refers to the value of that register during the first half cycle and the subscript 2 refers to the value during the second half cycle. the corresponding duty cycles are: ( ) ( ) ( ) ( ) d t t pwmcha pwmcha pwmdt pwmdt pwmtm pwmtm d t t pwmtm pwmtm pwmcha pwmcha pwmdt pwmdt pwmtm pwmtm ah ah s 1 2 1 2 1 2 al al s 1 2 1 2 1 2 1 2 = = + - - + = = + - - - - + since for the completely general case in double update mode, the switching period is given by:
a a admc401 - p reliminary t echnical i nformation a analog devices inc., proprietary & confidential 6/5/98 rev 2.1 - information subject to change page 37 of 74 ( ) t t s ck = + pwmtm pwmtm 1 2 again, the values of t ah and t al are constrained to lie between zero and t s . similar pwm signals to those illustrated in figure 9 and figure 10 can be produced on the bh, bl, ch and cl outputs by programming the pwmchb and pwmchc registers in a manner identical to that described for pwmcha. 6.2.6 special consideration for pwm operation in overmodulation the pwm timing unit is capable of producing pwm signals with variable duty cycle values at the pwm output pins. at the extremities of the modulation process, both 0% and 100% modulation are possible. these two modes are termed full off and full on respectively. in between, for other duty cycle values, the operation is termed normal modulation . full on: the pwm for any pair of pwm signals is said to operate in full on when the desired hi side output of the three-phase timing unit is in the on state (lo) between successive pwmsync pulses. this state may be entered by virtue of the commanded duty cycle values (in conjunction with the pwmdt register) or by virtue of the correct operation of the pulse deletion circuit. full off: the pwm for any pair of pwm signals is said to operate in full off when the desired hi side output of the three-phase timing unit is in the off state (hi) between successive pwmsync pulses. this state may be entered by virtue of the commanded duty cycle values (in conjunction with the pwmdt register) or by virtue of the correct operation of the pulse deletion circuit. normal modulation: the pwm for any pair of pwm signals is said to operate in normal modulation when the desired output duty cycle is other than 0% or 100% between successive pwmsync pulses. there are certain situation when transitioning either into or out of either full on or full off where it is necessary to insert additional dead time delays to prevent potential shoot through conditions in the inverter. the particular situation also depends on whether operation is in single or double update mode. in double update mode, it is also necessary to consider whether the pwm unit is transitioning from the first half cycle to the second half cycle or vica versa. the insertion of the additional dead time into one of the pwm signals of a given pair during these transitions is only needed if otherwise both pwm signals would be required to toggle at the pwmsync boundary. the additional dead time delay is inserted into the pwm signal that is toggling into the on state. in effect the turn on of this signal is delayed by an amount 2*pwmdt* t ck from the rising edge of pwmsync. after this delay, the pwm signal is allowed to turn on provided, the desired output is still the on state after the dead time delay. figure 11 illustrates two examples of such transitions where in figure 11 (a) when transitioning from normal modulation to full on at the half cycle boundary in double update mode, no special action is needed. however in figure 11 (b) when transitioning into full off at the same boundary, it can be seen that an additional dead time is necessary. clearly, this inserted dead time is a little different to the normal dead time as it is impossible to move one of the switching events back in time as this would take it into the previous modulation cycle. therefore, the entire dead time is inserted by delaying the turn on of the appropriate signal by the full amount. table 6 summarizes the different possible transitions into and out of full on and full off modes and the required actions. it can be seen that the transitions in double update mode at the full cycle boundary are identical to those of single update mode. mode transition operation dum normal to full on at half cycle boundary no action dum full on to normal at half cycle boundary no action
a a admc401 - p reliminary t echnical i nformation a analog devices inc., proprietary & confidential 6/5/98 rev 2.1 - information subject to change page 38 of 74 dum normal to full off at half cycle boundary insert dead time to al dum full off to normal at half cycle boundary insert dead time to ah dum/sum normal to full on at full cycle boundary insert dead time to ah dum/sum full on to normal at full cycle boundary insert dead time to al dum/sum normal to full off at full cycle boundary no action dum/sum full off to normal at full cycle boundary no action table 6 : summary of operations needed due to transitions into and out of full on and full off states of pwm controller. pwmtm pwmtm pwmcha 1 2*pwmdt ah al ah al dead time inserted (a) (b) full on full off 2*pwmdt figure 11 : examples of transitioning form normal modulation into either full on or full off where it may be necessary to insert additional dead times (a) transition from normal modulation to full on at half cycle boundary in double update mode where no additional dead time is needed (b) transition from normal modulation to full off at half cycle boundary in double update mode where additional dead time is inserted by the pwm controller of the admc401. 6.2.7 minimum pulse width, pwmpd register in many power converter switching applications, it is desirable to eliminate pwm switching signals below a certain width. it takes a certain finite time to both turn on and turn off power semiconductor devices. therefore, if the width of any of the pwm signals goes below some minimum value, it may be desirable to completely eliminate the pwm switching for that particular cycle. the allowable minimum pulsewidth for any of the six pwm outputs that can be produced by the pwm controller may be programmed using the 10-bit read/write pwmpd register. the minimum pulsewidth, t min is programmed in increments of 2t ck as: t pwmpd t min ck = 2 so that a pwmpd value of 0x00a defines a permissible minimum on-time of 0.77 m s for a 26 mhz clkout. the operation of the minimum pulsewidth control ensures that the time from turning on to turning off (or alternatively from turning off to turning on) any pwm signal is never less than the t min value as specified by the pwmpd register. if the pwm controller detects that the time between turning on and turning off any one pwm signal (say ah) is less than t min ,
a a admc401 - p reliminary t echnical i nformation a analog devices inc., proprietary & confidential 6/5/98 rev 2.1 - information subject to change page 39 of 74 the pwm pulse is deleted and the pwm signal remains completely off over the pwm period. the complementary signal, al in this case, is then turned completely on. 6.2.8 pwm timer operation the internal operation of the pwm generation unit is controlled by the pwm timer that is clocked at the dsp instruction rate, with period t ck . the operation of the pwm timer over one full pwm period is illustrated in figure 12 . it can be seen that during the first half cycle (sysstat bit 3 is cleared), the pwm timer decrements from pwmtm to 0. at this point, the count direction changes and the timer continues to increment to the pwmtm value. also shown in figure 12 are the pwmsync pulses for operation in both single and double update modes. clearly, an additional pwmsync pulse is generated at the mid-point of the pwm cycle in double update mode. of course, the value of the pwmtm register could be altered at the mid-point in double update mode. in such a case, the duration of the second half period (sysstat bit 3 is set) could be different to that of the first half cycle. sysstat (3) pwm timer decrements from pwmtm to 0 pwmtm 0 pwm timer increments from 0 to pwmtm t ck 1 pwmsync (sum) pwmsync (dum) figure 12 : operation of internal pwm timer of admc401. 6.2.9 startup of pwm controller it is important to fully understand the operation of the pwm controller during startup. following a power up or reset operation (either hardware of software), the pwm generation unit is placed in a lockoff state and all six pwm output signals (ah to cl) are placed in the off state (as defined by the pwmpol pin). the first write operation to any of the pwmtm, pwmcha, pwmchb or pwmchc registers will cause the pwm generation unit to transition to a disable state and the pwm timer begins to increment from zero. during this time all six pwm outputs are still in the off state and the pwmsync pulse is not produced. the pwm generation unit does not enter the normal state until all four of the pwmtm, pwmcha, pwmchb and pwmchc registers have been written to and the first load signal is generated. the load signal is generated each time the pwm timer reaches the value in the pwmtm register in single update mode. an additional load signal is generated in double update mode when the pwm timer reaches 0. the load signal is used to latch new values into each of the pwmtm, pwmcha, pwmchb, pwmchc, pwmdt, pwmpd, pwmseg and pwmsyncwt registers.
a a admc401 - p reliminary t echnical i nformation a analog devices inc., proprietary & confidential 6/5/98 rev 2.1 - information subject to change page 40 of 74 the operation during startup will be somewhat different depending on whether or not the pwmtm register is the first pwm register that is written. if the pwmtm register is written first, the pwm timer will begin incrementing from zero to the pwmtm value. this actually corresponds to the second half cycle (sysstat bit 3 is set) of the pwm as can be seen from figure 12 . during this time, the pwm unit is in the disable state and all six pwm outputs are off. provided the pwmcha, pwmchb and pwmchc registers have all been written to by the time the pwm timer reaches the pwmtm value, the first internal load signal is generated when the pwm timer reaches the pwmtm value. at this point the pwm generation unit enters the normal state and the new values are latched into the pwmcha, pwmchb and pwmchc registers. however, no pwmsync pulse is generated at this first load signal. the values written to the pwmcha, pwmchb and pwmchc registers (in conjunction with the other pwm registers such as the pwmdt, pwmpd, pwmseg, pwmgate registers) define the pwm outputs during the next pwm cycle (in single update mode) or the next half cycle (in double update mode). the appearance of the first pwmsync pulse (and associated interrupt) will occur at the end of this first pwm cycle in single update mode when the pwm timer again reaches the pwmtm value. the first pwmsync pulse and interrupt will occur at the mid-point of the first pwm cycle in double update mode when the pwm timer reaches zero. therefore, in single update mode the first pwmsync pulse will occur one and a half pwm periods or: t sum 1 1 5 2 , . = pwmtm t ck after the initial write to the pwmtm register. in double update mode the first pwmsync pulse appears one full pwm period or: t dum 1 1 0 2 , . = pwmtm t ck after the initial write to the pwmtm register. the startup operation of the pwm unit is illustrated in figure 13 for single update mode. the first pwm register that is written to is the pwmtm register that begins the incrementing of the timer from 0. it can be seen from figure 13 that both the ah and al outputs (as well as the bh, bl, ch and cl outputs) are in the off state during this initial half period. assuming an initial value of 0 is written to the pwmcha register (and some initial value is written to the other two duty cycle registers) prior to the pwm timer reaching the pwmtm value, the ah output stays in the off state and the al output goes to the full on state for the entire next pwm period. only at the end of this cycle is the first pwmsync pulse generated. therefore, if the values in the pwmtm and duty cycle registers have not changed, the al and ah signals will remain in the same state for the next pwm period. the startup operation of the pwm unit is illustrated in figure 14 where again it is assumed that the pwmtm register is written first and begins the timer incrementing from 0. again, the pwmcha duty cycle register is written with an initial value of 0, so that when the pwm timer reaches the pwmtm value, the ah signal remains in the off state and the al signal goes to fully on for the next pwm half cycle. at the end of this half cycle, when the pwm timer reaches zero, the first pwmsync pulse appears. at this stage, assuming the pwm duty cycle registers have been updated, the pwm signals transition to the appropriate duty cycle outputs, as given by the new duty cycle register value and the contents of the dead time register, as illustrated in figure 14 . again, it can be seen that because of the transition from full off to normal modulation at the first pwmsync pulse, an additional dead time is inserted into the ah output as dictated by the logic of table 6 . if the pwmtm register is not the first pwm register written to but instead either pwmcha, pwmchb or pwmchc is written first, then the operation is different to that described above. the act of writing to one of the duty cycle registers causes the pwm timer to begin incrementing prior to writing to the pwmtm register. the pwmtm register will thus contain its default reset value of 0. therefore, the first load signal would not be generated until the pwm timer increments to 0 (corresponding to a counter overflow from 0xffff). therefore, the pwmtm register will not be loaded with its initial
a a admc401 - p reliminary t echnical i nformation a analog devices inc., proprietary & confidential 6/5/98 rev 2.1 - information subject to change page 41 of 74 value until 65,535*t ck (2.52 ms at 26 mhz clkout) after the initial write to the first duty cycle register. therefore, it is recommended that the pwm system be initialized by first writing to the pwmtm register and immediately following with initial writes to the three duty cycle registers and any other appropriate configuration registers. pwm timer decrements from pwmtm to 0 pwmtm 0 pwm timer increments from 0 to pwmtm ah al pwmsync 1.5*2*pwmtm*t ck initial write to pwmtm write 0 to pwmcha, as well as initial value to pwmchb and pwmchc figure 13 : startup of pwm generation unit in single update mode (active hi pwm). pwm timer decrements from pwmtm to 0 pwmtm 0 pwm timer increments from 0 to pwmtm ah al pwmsync 1.0*2*pwmtm*t ck initial write to pwmtm write 0 to pwmcha, as well as initial value to pwmchb and pwmchc 2*pwmdt*t ck pwmcha*t ck update pwmcha value figure 14 : startup of pwm generation unit in double update mode (active hi pwm).
a a admc401 - p reliminary t echnical i nformation a analog devices inc., proprietary & confidential 6/5/98 rev 2.1 - information subject to change page 42 of 74 6.2.10 effective pwm resolution in single update mode, the same value of pwmcha, pwmchb and pwmchc are used to define the on-times in both half cycles of the pwm period. as a result the effective resolution of the pwm generation process if 2t ck (or 77 ns for a 26 mhz clkout) since incrementing one of the duty cycle registers by 1 changes the resultant on-time of the associated pwm signals by t ck in each half period (or 2t ck for the full period). in double update mode, improved resolution is possible since different values of the duty cycles registers are used to define the on-times in both the first and second halves of the pwm period. as a result, it is possible to adjust the on-time over the whole period in increments of t ck . this corresponds to an effective pwm resolution of t ck in double update mode (or 38.5 ns for a 26 mhz clkout). the achievable pwm switching frequency at a given pwm resolution is tabulated in table 7 . resolution (bits) single update mode pwm frequency (khz) double update mode pwm frequency (khz) 8 50.8 101.6 9 25.4 50.8 10 12.7 25.4 11 6.35 12.7 12 3.17 6.35 table 7 : achievable pwm resolution in single and double update modes (clkout = 26 mhz). 6.3 o utput c ontrol u nit , pwmseg r egister the operation of the output control unit is controlled by the 9-bit read/write pwmseg register that controls two distinct features that are directly useful in the control of ecm or bdcm. 6.3.1 crossover feature the pwmseg register contains three crossover bits; one for each pair of pwm outputs. setting bit 8 of the pwmseg register enables the crossover mode for the ah/al pair of pwm signals, setting bit 7 enables crossover on the bh/bl pair of pwm signals and setting bit 6 enables crossover on the ch/cl pair of pwm signals. if crossover mode is enabled for any pair of pwm signals, the high-side pwm signal from the timing unit (ah say) is diverted to the associated low-side output of the output control unit so that the signal will ultimately appear at the al pin. of course, the corresponding low- side output of the timing unit is also diverted to the complementary high-side output of the output control unit so that the signal appears at the ah pin. following a reset, the three crossover bits are cleared so that the crossover mode is disabled on all three pairs of pwm signals. care must be taken with the crossover feature to prevent potential shoot through conditions from developing in the power converter due to dead time violations. this situation is illustrated in figure 15 where operation in double update mode is assumed with active lo pwm signals. the channel a duty cycle register is altered for the second half cycle and it is assumed that the crossover mode is enabled for the second half cycle. figure 15 (a) illustrates the resultant pwm signals if the crossover mode is not enabled. figure 15 (b) shows the resultant signals if the ah and al signals are simple swapped by setting the crossover bit for channel a prior to the start of the second half cycle. clearly, this would cause both the al and ah signals to switch simultaneously at the mid point of the pwm cycle. this corresponds to a simultaneous command to turn off the ah switch and turn on the al switch. this violates the required dead time criterion and can cause potentially destructive short-circuit conditions in the power inverter. as a result, the pwm unit of the admc401 detects this condition and inserts an additional dead time delay into the pwm signals as illustrated in figure 15 (c).
a a admc401 - p reliminary t echnical i nformation a analog devices inc., proprietary & confidential 6/5/98 rev 2.1 - information subject to change page 43 of 74 the pwm unit of the admc401 inserts this additional dead time into the appropriate signals if it detects a change of state in any of the crossover bits at successive pwmsync boundaries. in other words, if the pwm unit detects that the channel a crossover bit is set at one pwmsync boundary and cleared at the next one (or vica versa), it inserts a dead time into the pwm signal that is to be turned on (either al or ah). of course, this may result in complete deletion of the pwm pulse if the duty cycle value is sufficiently small. also, the pwm block monitors the channel b and channel c crossover bits and performs similar operations on the bh, bl and ch, cl signals, respectively. it is important to recognize that such an action is necessary only when the crossover bit is toggled. if the crossover bit remains set or cleared for many pwm cycles, the added dead time is not necessary as all dead time insertions are taken care of by the normal operation of the three-phase timing unit. pwmtm pwmtm pwmcha 1 pwmcha 2 2*pwmdt 2*pwmdt ah al ah al dead time violation ah al dead time inserted 2*pwmdt (a) (b) (c) figure 15 : insertion of additional dead time due to crossover feature of pwm. (a) initial programmed pwm signals without crossover featured enabled (double update mode, active lo). (b) same pwm signals but with crossover mode enabled in second half cycle resulting in potential dead time violation at middle of pwm cycle (c) resultant pwm output signals of admc401 with added dead time to prevent potential problem outlined in (b). 6.3.2 output enable function the pwmseg register also contains six bits (bits 0 to 5) that can be used to individually enable or disable each of the six pwm outputs. the pwm signal of the al pin is enabled by setting bit 5 of the pwmseg register while bit 4 controls ah, bit 3 controls bl, bit 2 controls bh, bit 1 controls cl and bit 0 controls the ch output. if the associated bit of the pwmseg register is set, then the corresponding pwm output is disabled irrespective of the value of the corresponding duty cycle register. this pwm output signal will remain in the off state as long as the corresponding enable/disable bit of
a a admc401 - p reliminary t echnical i nformation a analog devices inc., proprietary & confidential 6/5/98 rev 2.1 - information subject to change page 44 of 74 the pwmseg register is set. this output enable function is implemented after the crossover function. following a reset, all six enable bits of the pwmseg register are cleared so that all pwm outputs are enabled by default. in a manner identical to the duty cycle registers, the pwmseg is latched on the rising edge of the pwmsync signal so that changes to this register only become effective at the start of each pwm cycle in single update mode. in double update mode, the pwmseg register can also be updated at the mid-point of the pwm cycle. 6.3.3 brushless dc motor (electronically commutated motor) control in the control of an ecm only two inverter legs are switched at any time and often the high-side device in one leg must be switched on at the same time as the low-side driver in a second leg. therefore, by programming identical duty cycles values for two pwm channels (say pwmcha = pwmchb) and setting bit 7 of the pwmseg register to crossover the bh/bl pair if pwm signals, it is possible to turn on the high-side switch of phase a and the low-side switch of phase b at the same time. in the control of ecm, it is usual that the third inverter leg (phase c in this example) be disabled for a number of pwm cycles. this function is implemented by disabling both the ch and cl pwm outputs by setting bits 0 and 1 of the pwmseg register. this situation is illustrated in figure 16 where it can be seen that both the ah and bl signals are identical, since pwmcha=pwmchb and the crossover bit for phase b is set. in addition, the other four signals (al, bh, ch and cl) have been disabled by setting the appropriate enable/disable bits of the pwmseg register. for the situation illustrated in figure 16 , the appropriate value for the pwmseg register is 0x00a7. in normal ecm operation, each inverter leg is disabled for certain periods of time, so that the pwmseg register is changed based on the position of the rotor shaft (motor commutation). pwmtm pwmtm pwmcha =pwmchb pwmcha =pwmchb 2*pwmdt 2*pwmdt ah al bl bh ch cl figure 16 : example active lo pwm signals suitable for ecm control, pwmcha=pwmchb, crossover bh/bl pair and disable al, bh, ch and cl outputs. operation is in single update mode.
a a admc401 - p reliminary t echnical i nformation a analog devices inc., proprietary & confidential 6/5/98 rev 2.1 - information subject to change page 45 of 74 6.4 g ate d rive u nit , pwmgate r egister 6.4.1 high frequency chopping the gate drive unit of the pwm controller adds features which simplify the design of isolated gate drive circuits for pwm inverters. if a transformer coupled power device gate drive amplifier is used then the active pwm signal must be chopped at a high frequency. the 10-bit read/write pwmgate register allows the programming of this high frequency chopping mode. the chopped active pwm signals may be required for the high-side drivers only, for the low-side drivers only or for both the high-side and low-side switches. therefore, independent control of this mode for both high and low-side switches is included with two separate control bits in the pwmgate register. typical pwm output signals with high-frequency chopping enabled on both high-side and low-side signals are shown in figure 17 . chopping of the high-side pwm outputs (ah, bh and ch) is enabled by setting bit 8 of the pwmgate register. chopping of the low-side pwm outputs (al, bl and cl) is enabled by setting bit 9 of the pwmgate register. the high frequency chopping frequency is controlled by the 8-bit word (gdclk) placed in bits 0 to 7 of the pwmgate register. the period of this high frequency carrier is: ( ) [ ] t 4 gdclk + 1 t chop ck = and the chopping frequency is therefore an integral subdivision of the clkout frequency: ( ) [ ] f f 4 gdclk + 1 chop clkout = the gdclk value may range from 0 to 255, corresponding to a programmable chopping frequency rate from 25.4 khz to 86.5 mhz for a 26 mhz clkout rate. the gate drive features must be programmed before operation of the pwm controller and typically are not changed during normal operation of the pwm controller. following a reset, all bits of the pwmgate register are cleared so that high frequency chopping is disabled, by default. pwmtm pwmtm pwmcha pwmcha 2*pwmdt 2*pwmdt ah al [4*(gdclk+1)] figure 17 : typical active lo pwm signals with high-frequency gate chopping enabled on both high-side and low-side switches (gdclk is integer equivalent of value in bits 0 to 7 of pwmgate register. 6.4.1 pwm polarity control, pwmpol pin the polarity of the pwm signals produced at the output pins ah to cl may be selected in hardware by the pwmpol pin. connecting the pwmpol pin to dgnd selects active lo pwm outputs, such that a lo level is interpreted as a command
a a admc401 - p reliminary t echnical i nformation a analog devices inc., proprietary & confidential 6/5/98 rev 2.1 - information subject to change page 46 of 74 to turn on the associated power device. conversely, connecting v dd to pwmpol pin selects active hi pwm and the associated power devices are turned on by a hi level at the pwm outputs. there is an internal pull-up on the pwmpol pin, so that if this pin becomes disconnected (or is not connected), active hi pwm will be produced. the level on the pwmpol pin may be read from bit 2 of the sysstat register, where a zero indicated a measured lo level at the pwmpol pin. 6.5 s witched r eluctance m ode the pwm block of the admc401 contains a switched reluctance mode that is controlled by the state of the pwmsr pin. the switched reluctance (sr) mode is enabled by connecting the pwmsr pin to dgnd. in this sr mode, the low-side pwm signals from the three-phase timing unit assume permanently on states, independent of the value written to the duty- cycle registers. the duty cycles of the high-side pwm signals from the timing unit are still determined by the three duty cycle registers. using the cross-over feature of the output control unit, it is possible to divert the permanently on pwm signals to either the high-side or low-side outputs. this mode is necessary because in the typical power converter configuration for switched or variable reluctance motors, the motor winding is connected between the two power switches of a given inverter leg. therefore, in order to build up current in the motor winding, it is necessary to turn on both switches at the same time. typical active lo pwm signals during operation in sr mode are shown in figure 18 for operation in double update mode. it is clear that the three low-side signals (al, bl & cl) are permanently on and the three-high-side signals are modulated in the usual manner so that the corresponding high-side power switches are switched between the on and off states. the sr mode can only be enabled by connecting the pwmsr pin to gnd. there is no software means by which this mode can be enabled. there is an internal pull-up resistor on the pwmsr pin so that if this pin is left unconnected or becomes disconnected the sr mode is disabled. of course, the sr mode is disabled when the pwmsr pin is tied to v dd . the state of this switched reluctance mode may be read from bit 4 of the sysstat register. if the pwmsr pin is hi (such that the sr mode is disabled) bit 4 of the sysstat register is cleared (indicating that the mode is disabled). conversely, if the pwmsr pin is lo and sr mode is enabled, bit 4 of sysstat is set. pwmtm pwmtm pwmcha 1 pwmcha 2 ah al bl bh ch cl pwmchb 1 pwmchb 2 pwmchc 1 pwmchc 2
a a admc401 - p reliminary t echnical i nformation a analog devices inc., proprietary & confidential 6/5/98 rev 2.1 - information subject to change page 47 of 74 figure 18 : active lo pwm signals in sr mode (pwmpol = pwmsr = dgnd) for admc401 in double update mode. the signals from the three-phase timing unit are not crossed over (pwmseg = 0) and the dead time is zero (pwmdt = 0). 6.6 pwm s hutdown in the event of external fault conditions, it is essential that the pwm system be instantaneously shutdown in a safe fashion. a falling edge on the pwmtrip pin provides an instantaneous, asynchronous (independent of the dsp clock) shutdown of the pwm controller. all six pwm outputs are placed in the off state (as defined by the pwmpol pin). in addition, the pwmsync pulse is disabled and the associated interrupt is stopped. the pwmtrip pin has an internal pull-down resistor so that if the pin becomes unconnected the pwm will be disabled. the state of the pwmtrip pin can be read from bit 0 of the sysstat register. the 12 pio lines of the admc401 can also be configured to operate as pwm shutdown pins using the piopwm register. the 12-bit piopwm has a control bit for each pio line (bit 0 control pio0 etc.). setting the control bit enables the corresponding pio line as a pwm shutdown pin. a falling edge on the pio line will then generate an instantaneous, asynchronous shutdown of the pwm system, in a manner identical to the pwmtrip pin. on power-up and following a reset, all pio lines are configured as inputs, have pull-downs and are programmed as pwm shutdown pins (piopwm = 0x0fff) so that the pwm is shutdown. correct operation of the pwm is not possible without first correctly configuring the pio system. in addition, it is possible to initiate a pwm shutdown in software by writing to the 1-bit read/write pwmswt register. the act of writing to this register generates a pwm shutdown command in a manner identical to the pwmtrip or pio pins. it does not matter which value is written to the pwmswt register. however, following a pwm shutdown, it is possible to read the pwmswt register to determine if the shutdown was generated by hardware or software. reading the pwmswt register automatically clears its contents. on the occurrence of a pwm shutdown command (either from the pwmtrip pin, the pio lines or the pwmswt register), a pwmtrip interrupt will be generated. in addition, the pwmsync pulse no longer appears at the output pin. however, internal operation of the pwm timer continues. following a pwm shutdown, the pwm can only be re-enabled (in a pwmtrip interrupt service routine, for example) by writing to all of the pwmtm, pwmcha, pwmchb and pwmchc registers. provided, the external fault has been cleared and the pwmtrip or appropriate pio lines have returned to a hi level, the pwm controller will restart in a manner identical to that following a power up, as described in section 6.2.7. 6.7 pwm r egisters the pwm registers are described in figure 19 .
a a admc401 - p reliminary t echnical i nformation a analog devices inc., proprietary & confidential 6/5/98 rev 2.1 - information subject to change page 48 of 74 pwmcha (r/w) pwmchb (r/w) pwmchc (r/w) dm (0x200c) dm (0x200d) dm (0x200e) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 pwmdt(r/w) dm (0x2009) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 pwmpd(r/w) dm (0x200a) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 pwmgate(r/w) dm (0x200b) gdclk low-side chopping high-side chopping 1=enable 0=disable ch enable cl enable bh enable bl enable ah enable al enable 1=disable 0=enable ah/al crossover bh/bl crossover ch/cl crossover 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 pwmseg(r/w) dm (0x200f) 0 0 0 0 0 0 0 0 0 1=enable 0=disable 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 pwmsyncwt(r/w) dm (0x2060) 0 0 1 0 0 1 1 1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 pwmswt(r/w) dm (0x2061) 0 pwmtm (r/w) dm (0x2008) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 figure 19 : structure of pwm registers of admc401 (shaded bits are unused, reset values included, where defined).
a a admc401 - p reliminary t echnical i nformation a analog devices inc., proprietary & confidential 6/5/98 rev 2.1 - information subject to change page 49 of 74 7. encoder interface unit. 7.1 o verview the admc401 incorporates a powerful encoder interface block to incremental shaft encoders, that are often used for position feedback in high performance motion control systems. the functional block diagram of the entire encoder interface system of the admc401 is shown in figure 20 . the encoder interface unit (eiu) includes a 16-bit quadrature up/down counter, programmable input noise filtering of the encoder input signals and the zero markers, and has four dedicated pins on the admc401. the quadrature encoder signals are applied at the eia and eib pins. alternatively, a frequency and direction set of inputs may be applied to the eia and eib pins. in addition, two zero marker/strobe inputs are provided on pins eizp and eis. these inputs may be used to latch the contents of the encoder quadrature counter into dedicated registers, eizplatch and eislatch, on the occurrence of external events at the eizp and eis pins. these events may be programmed to be either rising edge only (latch event) or rising edge if the encoder is moving in the forward direction and falling edge if the encoder is moving in the reverse direction (software latched zero marker functionality). the encoder interface unit incorporates programmable noise filtering on the four encoder inputs to prevent spurious noise pulses from adversely affecting the operation of the quadrature counter. the encoder interface unit operates at a clock frequency equal to half of the dsp instruction rate, clkout, so that the fundamental time increment is 2*t ck (or 77 ns for a 26 mhz clkout). the encoder interface unit operates correctly with encoder signals at frequencies of up to 3.25 mhz. the eiu may be programmed to use the zero marker on eizp to reset the quadrature encoder in hardware, if required. alternatively, the zero marker can be ignored and the encoder quadrature counter is reset according to the contents of a maximum count register, eiumaxcnt. there is also a ?single north marker? mode available in which the encoder quadrature counter is reset only on the first zero marker pulse. both modes are enabled by dedicated control bits in the eiu control register, eiuctrl. a status bit is set in the eiustat register on the first occurrence of the zero marker. the encoder interface unit can also be made to implement some error checking functions. if the error checking mode is enabled, upon the occurrence of a zero pulse, the contents of the encoder counter register are compared with the expected value (0 or eiumaxcnt depending on the direction of rotation). if an encoder count error is detected (say due to a disconnected encoder line), a status bit in the eiustat register is set and an eiu count error interrupt is generated. an additional status bit is provided in the eiustat register that indicates the initialization state of the eiu. until the eiumaxcnt register is written to, the eiu is not initialized. three status bit in the eiustat register can also be read to read the state of the three eiu pins, eia, eib and eizp. the encoder interface unit of the admc401 contains a 16-bit loop timer that behaves in a manner similar to the programmable interval timer of the dsp core. the loop timer consist of a timer register, period register and scale register so that it can be programmed to time-out and reload at appropriate intervals. a control bit in the eiuctrl register is used to enable/disable this loop timer. when this loop timer times out, an eiu loop timer timeout interrupt is generated. this interrupt could be used to control the timing of speed and position control loops in high-performance drives. the encoder interface unit also includes a high-performance encoder event timer (eet) block that permits the accurate timing of successive events of the encoder inputs. the eet can be programmed to time the duration between up to 255 encoder pulses and can be used to enhance velocity estimation, particularly at low speeds of rotation. the information from the registers of the eet block can be latched in two ways. in one mode, the contents of the eiu quadrature count register, eiucnt and all relevant eet registers (eett and eetdeltat) are latched when the eiu timer times-out. in the second mode, the act of reading the eiucnt register also simultaneously latches the eet registers. the eet data latching mode is selected by a control bit in the eiuctrl register.
a a admc401 - p reliminary t echnical i nformation a analog devices inc., proprietary & confidential 6/5/98 rev 2.1 - information subject to change page 50 of 74 noise filtering eia eib eis 16-bit quadrature up/down counter eiuctrl(5::0) eiucnt(15::0) encoder counter error checking a b s eiumaxcnt(15::0) zero rev eiustat(2::0) eiu interrupts dsp data memory bus encoder event timer pulse decimator quadrature signal eetn(7::0) direction eett(15::0) eetdeltat(15::0) eetdiv(15::0) clock divider clk clkout eetstat(0) encoder interface block encoder event timer block snm mon eiustat(5::3) eiutimer (15:0) eiuscale (7:0) eiuperiod(15:0) timeout encoder loop timer eetcnt(15::0) eiufilter(8::0) latch eizp eizplatch(15::0) eislatch(15::0) zp figure 20 : configuration of encoder interface system of admc401 . 7.2 e ncoder l oop t imer the eiu contains a 16-bit loop timer that is structured in a manner similar to the interval timer of the dsp core (tcount, tperiod and tscale registers). the corresponding registers of the encoder loop timer are the 16-bit read/write eiutimer and eiuperiod and the 8-bit read/write eiuscale register. the eiu loop timer is clocked at the clkin rate, t cki . the eiu loop timer can be used to generate periodic interrupts based on multiples of the clkin cycle times. the eiu loop timer is enabled by setting bit 5 of the eiuctrl register. when enabled, the 16-bit timer register (eiutimer) is decremented every n cycles, where n-1 is the scaling value stored in the 8-bit eiuscale register. when the value of the eiutimer register reaches zero and eiu loop timer time-out interrupt is generated and the eiutimer register is reloaded with the 16-bit value in the eiuperiod register. the scaling feature of this timer, provided by the eiuscale register, allows the 16-bit timer to generate periodic interrupts over a wide range of periods. for a 26 mhz clkout rate (38.5 ns period), the timer can generate interrupts with periods of 77 ns up to 5.04 ms with a zero scale value (eiuscale = 0). when scaling is used, time periods can range up to 1.29 s. the eiu loop timer time-out interrupt can be masked in the picmask register.
a a admc401 - p reliminary t echnical i nformation a analog devices inc., proprietary & confidential 6/5/98 rev 2.1 - information subject to change page 51 of 74 7.3 e ncoder i nterface s tructure & o peration 7.3.1 introduction the encoder interface section consists of 16-bit quadrature up/down counter, a 16-bit read/write eiucnt register that allows the up/down counter to be read by the dsp. there is also a 16-bit read/write eiumaxcnt register that must be written to initialize the encoder system. until the eiumaxcnt register has been written to, the encoder interface unit is not initialized and bit 2 of the eiustat register is set. the contents of the eiumaxcnt register are used in certain operating modes to reset the quadrature counter. the contents of the eiumaxcnt register are also used for error checking of the eiu. operation of the encoder interface is controlled by the read/write eiuctrl register. 7.3.2 input noise filtering of encoder signals a functional block diagram of the input stages of the encoder interface is shown in figure 21 . the four encoder input signals (eia, eib, eizp & eis) are first synchronized to the clkout rate in input synchronization buffers. this eliminates the asynchronous nature of real world encoder signals prior to use in the encoder interface unit logic. subsequently, all three synchronized signals (eias, eibs, eizps & eiss) are applied to programmable noise filtering circuits that can be programmed to reject pulses that are shorter than some suitable programmed value. the outputs of the filter stage are applied to the quadrature counter stage. eiufilter (5::0) eia eib input synchron- ization stage clkout clock divide three stage delay filter a b eias eibs eis s eiss eizp zp eizps figure 21 : functional block diagram of inputs stage (synchronization and noise filtering of encoder interface). each of the four synchronized input signals (eias, eibs, eizps and eiss) is applied to a three clock cycle delay filter such that the filtered output signals are not permitted to change until a stable value has been registered for three successive clock cycles. while the encoder signals are changing, the filter maintains the previous output value. the clock frequency used for the filter circuits is programmed by bits 0 to 5 of the eiufilter register. the 6-bit quantity written to bits 0 to 5 of the eiufilter register is used to divide the clkout frequency and provide the clock source for the encoder noise filters. if the value written to bits 0 to 5 of the eiufilter register is n, the period of the clock source used in the encoder filters is (n+1)*t ck . therefore, the minimum pulse width that can be accepted on the encoder signals is three of these clock periods or:
a a admc401 - p reliminary t echnical i nformation a analog devices inc., proprietary & confidential 6/5/98 rev 2.1 - information subject to change page 52 of 74 ( ) t 3 n + 1 t minenc ck = for example, writing a value of 3 to bits 0 to 5 of the eiufilter register, means that clock frequency used in the encoder filters is 6.5 mhz (for a clkout rate of 26 mhz). in order to register as a stable value, the encoder input signals must be stable for three of these 6.5 mhz cycles (or 462 ns). consequently, the smallest period that will be registered on the synchronized encoder inputs is 924 ns, corresponding to a maximum encoder rate of 1.08 mhz. in general, the maximum encoder rate that can be recognized is given by: ( ) f f n encmax clkout = + 6 1 operation of both the input synchronization logic and the noise filters is shown in figure 22 for the default case where eiufilter(5::0) = 0x00 and the noise filters are clocked at clkout. clkout t ck eia eib noise pulse eias eibs a b 3t ck 3t ck figure 22 : operation of input synchronization and noise filters of encoder interface with eiufilter(5:0) = 0x00 such that the filters are operated at clkout. the default value for eiufilter(5::0) following a power on reset is 0x00 so that the eiu filters are clocked at the clkout rate and minimal filtering is applied. there is a direct trade-off between the amount of filtering applied to the encoder inputs and the maximum possible encoder signal rate. in effect, the larger the value of eiufilter(5::0), the more filtering that is applied to the encoder signals so that, for a given number of encoder lines, the maximum speed of rotation is lower. the maximum encoder signal rate and minimum permissible encoder pulse width are tabulated in table 8 for different values of eiufilter(5::0).
a a admc401 - p reliminary t echnical i nformation a analog devices inc., proprietary & confidential 6/5/98 rev 2.1 - information subject to change page 53 of 74 eiufilter (5::0) encoder filter clock frequency (mhz) minimum pulse width (ns) maximum encoder rate (mhz) 0 (default) 26 115.5 4.3 1 13 231 2.1 2 8.667 346.5 1.44 3 6.5 462 1.08 4 5.2 577.5 0.865 : : : : 63 0.406 7392 0.067 table 8 : minimum permissible encoder pulse width and corresponding maximum encoder signal rate for different value of eiufilter(5:0) assuming a clkout rate of 26 mhz. the influence of the encoder filter can be on the zero marker signals (eizps and eiss) can be somewhat different that on the eias or eibs signals, depending on the exact nature of the encoder. in common incremental encoders, the width of the zero marker can be equal to a quarter, a half or a full period of one of the quadrature signals (say eia). applying the three- stage delay filter to a zero marker whose width is either equal to half or a full quadrature pulse period does not change the achievable maximum encoder rate. however, the maximum possible encoder rate is changed if the three-stage filter is applied in the case where the width of the zero marker is equal to a quarter of the eia or eib period. in this case the influence of the three-stage delay filter is to effectively half the maximum encoder signal rate to that described above (or 1.625 mhz for a 26 mhz clkout rate). 7.3.3 encoder quadrature counter operation following the input synchronization stages the a and b encoder signals (filtered outputs) go to a state machine that determines the appropriate actions for the quadrature counter, eiucnt. essentially, the state machine consists of dual flip- flops on each of the a and b inputs so that the logic can detect change of state events at each input, as illustrated in figure 23 . the action demanded by the state machine depends on the present state of both encoder inputs (new_a and new_b) as well as the state of both inputs in the previous clock cycle (last_a and last_b). four possible outcomes are possible from the state machine: count up: the eiu quadrature counter is incremented by 1. count down: the eiu quadrature counter is decremented by 1. no count: no change of state event has been detected and no action is taken at the quadrature counter. error: this is an illegal state (possibly occurs if the encoder signals exceed the maximum data rate). if this event is detected, the no count action is performed. the actions taken by the encoder quadrature counter are summarized in table 9 .
a a admc401 - p reliminary t echnical i nformation a analog devices inc., proprietary & confidential 6/5/98 rev 2.1 - information subject to change page 54 of 74 a last_a new_a latch latch b last_b new_b latch latch clkout clkout state machine count up count down no count error figure 23 : structure of eiu input state machine. new_a last_a new_b last_b action 0 0 0 0 no count 0 0 0 1 count up 0 0 1 0 count down 0 0 1 1 no count 0 1 0 0 count up 0 1 0 1 error 0 1 1 0 error 0 1 1 1 count down 1 0 0 0 count up 1 0 0 1 error 1 0 1 0 error 1 0 1 1 count down 1 1 0 0 no count 1 1 0 1 count down 1 1 1 0 count up 1 1 1 1 no count table 9 : summary of appropriate quadrature counter operations. 7.3.4 encoder counter direction the direction of quadrature counting is determined by bit 0 (rev) of the eiuctrl register. if the rev bit is cleared the signal at the eia pin is fed to the a input to the quadrature counter and the eib pin is fed to the b input. thus, if the eia-
a a admc401 - p reliminary t echnical i nformation a analog devices inc., proprietary & confidential 6/5/98 rev 2.1 - information subject to change page 55 of 74 encoder signal leads the eib-signal (and therefore the a signal leads the b signal), the quadrature counter is incremented on each edge, as shown in figure 24 . this (a signal leads the b signal) is defined as the forward direction of motion. setting bit 0 of the eiuctrl register causes the signal at the eia pin to be fed to the b input to the quadrature counter and the signal eib becomes the b input to the quadrature counter. therefore, if the eia signal led the eib signal at the pins of the admc401, the a input to the quadrature counter will now lag the b input. this will be recognized as rotation in the reverse direction and the counter will be decremented on each quadrature pulse. following a reset, the rev bit is cleared. as shown in figure 20 , the two encoder signals are used to derive a quadrature signal that is used, in conjunction with a direction bit, to increment or decrement the encoder counter and also the encoder event timer. the derivation of these signals results from the output of the state machine described in table 9 . the status of the direction signal is indicated at bit 1 of the eiustat register. while the encoder counter is incrementing, bit 1 is set. alternatively, when the encoder counter is decrementing, bit 1 of the eiustat register is cleared. a b eiucnt quadrature signal velocity events encoder event timer value eet latch event eett eetdeltat figure 24 : operation of encoder interface unit and eet of admc401 in the forward direction with eetn = 2. 7.3.5 alternative frequency and direction inputs instead of the quadrature eia and eib encoder inputs, the encoder interface unit can also accept alternative frequency and direction inputs. this mode is enabled by setting bit 6 of the eiuctrl register. in this so-called fd mode , the eia input pin accepts a frequency signal and the eib pin accepts the direction signal. the signal on these pins are subject to the same synchronization and filtering logic as described previously. however, in this mode, the operation of the state machine is bypassed and the quadrature counter is incremented or decremented on each rising edge of the signal on the eia pin. if the eib pin is hi, forward operation is assumed and the counter is incremented on each rising edge of the frequency signal on the eia input. on the other hand, if the eib pin is lo, reverse rotation is assumed and the quadrature counter is decremented by one at each rising edge of the signal on the eia pin. on power-up or reset, bit 6 of the eiuctrl register is cleared so that this mode is disabled by default.
a a admc401 - p reliminary t echnical i nformation a analog devices inc., proprietary & confidential 6/5/98 rev 2.1 - information subject to change page 56 of 74 7.3.6 encoder counter reset the zero bit (bit 1) of the eiuctrl register determines if the encoder zero marker is used to hardware reset the up/down counter of the encoder interface. when bit 1 of the eiuctrl register is set, the zero marker signal on eizp is used to reset the up/down counter to zero (if moving in the forward direction) or to the value in the eiumaxcnt register (if moving in the reverse direction). the reset operation takes place on the next quadrature pulse after the zero marker has been recognized. in order to ensure correct encoder counting (no missing or spurious codes) the logic in the encoder counter latches the conditions (appropriate encoder edge) at which the first reset is performed. thereafter, irrespective of operating conditions the encoder reset operation is always aligned with the same encoder edge. for example, if the first reset operation occurs on the rising edge of b and the encoder is moving in the forward direction, then all subsequent reset operations are aligned with the rising edge of the b signal (while moving in the forward direction) and on the falling edge of b for rotation in the reverse direction. in order to account for zero marker signals of different widths, the zero marker will be recognized as the rising edge of the eizp signal when moving in the forward direction. when moving in the reverse direction, the zero marker is recognized at the falling edge of the signal at the eizp pin. when the zero bit of the eiuctrl register is cleared, the zero marker is not used to reset the counter. in this mode, the contents of the eiumaxcnt register are used as the reset value for the up/down counter. for example, for an n-line incremental encoder, the appropriate value to write to the eiumaxcnt register is 4n-1. therefore, for a 1024 line encoder, a value of 0x0fff (= 4095) would be written to the eiumaxcnt register. however, since absolute position information is not available in this mode, due to the absence of the zero marker, the full 16-bit range of the quadrature counter may be employed by writing a value of 0xffff to the eiumaxcnt register. following a reset, the zero bit is cleared. the value written to the eiumaxcnt register must be in the form 4n - 1, where n is any integer . 7.3.7 latch/freeze/software zero marker inputs the encoder interface unit of the admc401 provides two marker signals, eizp and eis that are both filtered and synchronized in a manner identical to the other encoder signals to produce the zp and s signals. zp can be used as a hardware reset of the encoder counter. however, in many application a hardware reset of the counter may not be desirable because of disastrous effects that could occur due to incorrect resetting of the counter. instead, the encoder counter can be programmed to operate in full 16-bit rollover mode, by clearing bit 1 of the eiuctrl register and programming eiumaxcnt to be 0xffff. in this case, the quadrature counter will use the full 16-bit range of the eiucnt register. the signals on zp and s can be configured to latch the contents of the eiucnt register into dedicated memory mapped registers (eizplatch for zp and eislatch for s) on the occurrence of definite events on these pins. the exact nature of the events are determined by bit 7 of the eiuctrl register for zp and bit 8 of the eiuctrl register for s. if bit 7 of the eiuctrl register is cleared, the contents of the eiucnt register are latched to the eizplatch register on the occurrence of a rising edge on the zp signal. in this mode, the signals can be used to latch or freeze the eiucnt contents on the occurrence of an external event such as that from limit switches or other triggers. if bit 7 of the eiuctrl register is set, then the eiucnt contents are latched to the eizplatch register on the rising edge of the zp signal if the quadrature counter is incrementing (count up). if the quadrature counter is decrementing the eiucnt contents are latched to the eizplatch register on the falling edge of the zp signal. in this mode, the action resembles that of a zero marker function and the encoder index pulse could be applied to eizp. the advantage is that the eiucnt register contents are latched at the appropriate zero marker inputs but the contents of the quadrature counter are no affected. bit 8 of the eiuctrl register defines the s events that cause the eiucnt register to be latched to the eislatch register in an identical manner to that described for bit 7 above. eizplatch and eislatch are 16-bit read only registers whose state is undefined on power up. on power-up or following a reset, both bit 7 and 8 of the eiuctrl register are cleared so that freeze mode is enabled.
a a admc401 - p reliminary t echnical i nformation a analog devices inc., proprietary & confidential 6/5/98 rev 2.1 - information subject to change page 57 of 74 7.3.8 single north marker mode a further reset mode is available in the encoder interface unit called single north marker mode . this mode is enabled by setting bit 2 (snm) of the eiuctrl register. for this mode to operate the zero bit (bit1) of the eiuctrl register must also be set in this mode, the eiucnt register is reset (to zero or eiumaxcnt depending on direction) only on the first occurrence of the zero marker. subsequently, the eiucnt register is reset by the natural roll-over to zero or the value in the eiumaxcnt register. following a reset, this snm bit is cleared. bit 6 of the eiustat register is used to signal the first occurrence of a zero marker. when the first zero marker has been recognized by the eiu, bit 6 of the eiustat register is set. 7.3.9 encoder error checking error checking in the eiu is enabled by setting bit 3 (mon) of the eiuctrl register. the zero bit of the eiuctrl register must also be set for error checking to be enabled. in this mode, the contents of the eiucnt register are compared with the expected value (zero or eiumaxcnt depending on direction) when the zero marker is detected. if a value other than the expected value is detected, an error condition is generated by setting bit 0 of the eiustat register and triggering an eiu count error interrupt. this eiu count error interrupt is also managed and may be masked by the programmable interrupt controller (pic) block. the encoder continues to count encoder edges after an error has been detected. bit 0 of the eiustat register is cleared on the occurrence of the next zero marker provided the error condition no longer exists and the eiucnt register again matches the expected value. following a reset, the mon bit is cleared. 7.3.10 encoder pin status there are three additional status bits provided in the eiustat register that provide a measure of the state of the three eiu pins following the synchronization buffers (eias, eibs and eizps signals). bit 3 indicates the state of the eias signal, bit 4 indicates the state of the eibs signal and bit 5 gives the state of the eizps signal. the value of these status bits read is not affected by any of the control bits in the eiuctrl register. 7.4 e ncoder e vent t imer 7.4.1 introduction & overview the encoder event timer block forms an integral part of the eiu of the admc401. the eet accurately times the duration between encoder events. the information provided by the eet may be used to make allowances for the asynchronous timing of encoder and dsp-reading events. as a result, more accurate computations of the position and velocity of the motor shaft may be performed. the eet consists of a 16-bit encoder event timer, an encoder pulse decimator and a clock divider as shown in figure 20 . the eet clock frequency is selected by the 16-bit read/write eetdiv clock divide register, whose value divides the clkin frequency. the contents of the encoder event timer are incremented on each rising edge of the divided clock signal. an eetdiv value of zero gives the maximum divide value of 0x10000 (= 65,536), so that the clock frequency to the encoder event timer is at its minimum possible value. the quadrature signal from the encoder interface unit is decimated at a rate determined by the 8-bit read/write eetn register. for example, writing a value of 2 to eetn, produces a pulse decimator output train at half the quadrature signal frequency, as shown in figure 24 . the rising edge of this decimated signal is termed a velocity event. therefore, for an eetn value of 2, a velocity event occurs every two encoder edges, or on each edge of one of the encoder signals. an eetn value of 0 gives an effective pulse decimation value of 256.
a a admc401 - p reliminary t echnical i nformation a analog devices inc., proprietary & confidential 6/5/98 rev 2.1 - information subject to change page 58 of 74 on the occurrence of a velocity event, the contents of the encoder event timer are stored in an intermediate interval time register. under normal operation, this register stores the elapsed time between successive velocity events. after, the timer value has been latched at the velocity event, the contents of the encoder event timer are reset to one. 7.4.2 latching data from the eet when using the data from the encoder event timer, it is important to latch a triplet set of data at the same instant in time. the three pieces of data are the contents of the encoder quadrature up/down counter, the stored value in the interval time register (giving the precise measured time between the last two velocity events) and the present value of the encoder event timer (giving an indication of how much time has passed since the last velocity event). the data from the eet can be latched on the occurrence of two different events. the particular event is selected by bit 4 (eetlatch) of the eiuctrl register. setting this eetlatch bit causes the data to be latched on the time-out of the encoder loop timer (eiutimer). at that time, the contents of the encoder quadrature counter (eiucnt) are latched to a 16-bit, read-only register eetcnt. in addition, the contents of the intermediate interval time register are latched to the eett register and the contents of the encoder event timer are latched to the eetdeltat register. the three registers, eetcnt, eett and eetdeltat then contain the desired triplet of position/speed data required for the control algorithm. in addition, if the time-out of the eiutimer is used to generate an eiu loop timer interrupt, the required data is automatically latched and waiting for execution of the interrupt service routine (which may be some time after the time-out instant if there are multiple interrupts in the system). by latching the eiucnt register to the eetcnt, the user does not have to worry about changes in the eiucnt register (due to additional encoder edges) prior to servicing of the eiu loop timer interrupt. the other eet latch event is defined by clearing the eetlatch bit of the eiuctrl register. in this mode, whenever, the eiucnt register is read by the dsp, the current value of the intermediate interval time register are latched to the eett register and the contents of the encoder event timer are latched to the eetdeltat register. the three registers, eiucnt, eett and eetdeltat now contain the desired triplet of position/speed data required for the control algorithm. note the difference from before in that the encoder count value is now available in the eiucnt register. it is important to realize that the eett and eetdeltat registers is only updated by either the time-out of the eiutimer register (if eetlatch bit is set) or the act of reading the eiucnt register (if the eetlatch bit is cleared). therefore if the eetlatch bit is set, the act of reading the eiucnt register will not update the eett and eetdeltat registers. following a reset, bit 4 of the eiuctrl is cleared. 7.4.3 eet status register there is a 1-bit eetstat register that indicates whether or not an overflow of the eet has occurred. if the time between successive velocity events is sufficiently long, it is possible that the encoder event timer will overflow. when this condition is detected, bit 0 of the eetstat register is set and the eett register is fixed at 0xffff. reading the eetstat register clears the overflow bit and permits the eett register to be updated at the next velocity event. if an encoder direction reversal is detected by the eiu, the encoder event timer is set to zero and the eett register is set to its maximum 0xffff value. subsequent velocity events will cause the eett register to be updated with the correct value. if a value of 0xffff is read from the eett register, bit 0 of the eetstat register can be read to determine whether an overflow or direction reversal condition exists. in the case of a direction reversal, the contents of the eetdeltat register is valid, representing the time from the direction reversal to the instant at which the eiucnt register is read. on reset the eetn, eetdiv, eetdeltat and eett registers are all cleared to zero. whenever either the eetn or eetdiv registers are written to, the encoder event timer is reset to zero and the eett register is set to zero.
a a admc401 - p reliminary t echnical i nformation a analog devices inc., proprietary & confidential 6/5/98 rev 2.1 - information subject to change page 59 of 74 7.5 eiu/eet i nterface , p ins and r egisters the eiu and eet registers are illustrated in figure 25 , figure 25 , and figure 27 .
a a admc401 - p reliminary t echnical i nformation a analog devices inc., proprietary & confidential 6/5/98 rev 2.1 - information subject to change page 60 of 74 eiucnt (r/w) eiumaxcnt (r/w) eiuperiod (r/w) eiutimer (r/w) eetcnt (r) dm (0x2020) dm (0x2021) dm (0x2024) dm (0x2026) dm (0x2027) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 eiuscale (r/w) dm (0x2025) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 eiustat (r) dm (0x2022) eizp1 state eib state eia state 1=hi 0=lo eiu count error 1=error 0=no error eiu count direction 1=up 0=down eiu state 1=not initialized 0=initialized 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 eiuctrl (r/w) dm (0x2023) 0 0 0 0 0 0 0 0 0 direction reverse 1=swap eia and eib 0=do not swop eia/eib zero marker 1=use for reset 0=do not use single north marker mode 1=enable 0=disable enable eiu loop timer 1=enable 0=disable eet latch definition 1=eiutimer timeout 0=eiucnt read eiu error monitoring 1=enable 0=disable first zero marker 1=received 0=not received eis latch definition 1=zero marker 0=freeze input frequency & direction mode 1=enable 0=disable eizp latch definition 1=zero marker 0=freeze input figure 25 : structure of eiu registers of admc401 (shaded bits are unused, reset values included, where defined).
a a admc401 - p reliminary t echnical i nformation a analog devices inc., proprietary & confidential 6/5/98 rev 2.1 - information subject to change page 61 of 74 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 eiufilter(r/w) dm (0x2028) 0 0 0 0 0 0 encoder filter clock divide value eizplatch (r) eislatch (r) dm (0x2029) dm (0x202a) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 figure 26 : structure of eiu registers of admc401 (shaded bits are unused, reset values included, where defined). eetdiv (r/w) eetdeltat (r) eett (r) dm (0x2071) dm (0x2072) dm (0x2073) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 eetn (r/w) dm (0x2070) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 eetstat (r) dm (0x2074) eet overflow 1=overflow 0=no overflow 0 figure 27 : structure of eet registers of admc401 (shaded bits are unused, reset values included, where defined).
a a admc401 - p reliminary t echnical i nformation a analog devices inc., proprietary & confidential 6/5/98 rev 2.1 - information subject to change page 62 of 74 8. 0 programmable digital input/output. 8.1 o verview the admc401 has 12 programmable digital input/output pins called pio0 to pio11. each pin may be individually configured as either an input or an output. an associated data register may be used to read data from pins configured as inputs and write data to pins configured as outputs. in addition, each i/o line may be configured as an interrupts source. both edge (rising and falling) and level (high and low) interrupts may be detected. four of the pio lines (pio0 to pio3) have dedicated vector addresses in the interrupt table. the remaining eight interrupts (pio4 to pio11) are multiplexed into a single additional interrupt vector location. the pioflag register is used to determine which line caused the interrupt. in addition, all pio lines may be alternatively configured as pwm trip sources. the piopwm register has dedicated bits that may be used to enable this function on each pio line. in this mode, a low level on any pins configured as a pwm trip source shuts down the pwm in a manner identical to the pwmtrip pin. 8.2 pio c onfiguration each of the 12 programmable input/output lines may be configured as either an input or an output by programming the appropriate bits of the piodir register. this 12-bit read/write register has one bit associated with each i/o line; bit 0 corresponds to pio0 etc. clearing a bit in the piodir register will configure the corresponding pin as an input line. conversely, setting a bit configures the pin as an output pin. on reset, bits of the piodir register are cleared so that all 12 pio pins are configured as inputs. in addition, all pio lines are internally pulled down in the admc401 so that unconnected lines are seen as low-level inputs. 8.3 pio d ata r eading /w riting associated with the pio system is a data register, piodata, that also has a bit associated with each i/o line. data written to the piodata register will appear on those pins configured as outputs. in addition, reading the piodata register will read the data from those pins configured as inputs. 8.4 pio i nterrupt g eneration each of the 12 pio lines may be configured as an interrupt source. four of the pio lines, pio0 to pio3, have dedicated interrupt vector locations while the remaining eight are multiplexed into an additional interrupt vector. the piointen enable function is used to enable or disable the interrupt mode on the pio4 to pio11 lines. the picmask register of the programmable interrupt controller is used to enable interrupts on the four dedicated pio lines, pio0 to pio3. interrupts may be generated on either edge (rising or falling) or level (high or low) events by programming the appropriate bits of both the piomode and piolevel registers. both registers have a dedicated bit for each of the twelve pio lines. setting the appropriate bit of the piomode register configures the interrupt as level sensitive while clearing the bit set the interrupt for edge sensitive. in level-sensitive mode (piomode bit is 1), setting the corresponding bit in the piolevel register configures the interrupt as active high while clearing the bit in the piolevel register configures it for active low. in edge-sensitive mode (piomode bit is 0), setting the corresponding bit of the piolevel register configures the interrupt for rising edge, while clearing the bit configures the interrupt for falling edge. on reset all pio interrupts are disabled.
a a admc401 - p reliminary t echnical i nformation a analog devices inc., proprietary & confidential 6/5/98 rev 2.1 - information subject to change page 63 of 74 the four dedicated pio interrupts from pio0 to pio3 have interrupt vector addresses at program memory addresses 0x44 for pio0, 0x48 for pio1, 0x4c for pio2 and 0x050 for pio3. in the event of an interrupt on pio4 to pio11, the corresponding bit of the pioflag register is set and the general pio interrupt is activated. this interrupt has a dedicated vector address at location 0x3c. in the interrupt service routine for this interrupt, the user must poll the pioflag register to determine which of the pio4 to pio11 lines, that have interrupts enabled, caused the interrupt. of course, if only one of the pio4 to pio11 lines has interrupts enabled, no polling is necessary. pio lines that are configured as outputs may also be used to generate interrupts. if, for example, one of the pio lines is configured simultaneously as an output and as an interrupts source, writing the appropriate data sequence to that line will trigger an interrupt. 8.5 pio as pwm t rip s ources by setting the appropriate bits of the piopwm register, each of the twelve pio lines can be configured as a pwm trip source. in this mode, a low-level on the pio pin will cause a pwm trip that will disable all six pwm outputs on ah to cl. the disabling of the pwm is independent of the dsp clock, so that the pwm stage can be fully protected even in the event of a loss of clock signal to the dsp. in addition, a pwmtrip interrupt will be generated when the pwm is reset. however, it is also possible to generate the normal pio interrupts on the occurrence of a falling-edge on the pio line. the advantage of this highly flexible structure for pwm shutdown is that multiple fault signals could be applied to the admc401 at different pio lines. the occurrence of a falling-edge on any of them will instantaneously shut down the pwm. however, based on the particular pio interrupt that is flagged, the user can easily determine the source of the trip. this permits the action of the interrupt service routines following a pwm trip to be tailored to the particular fault that occurred. on reset, all pio lines are configured as pwm trip sources. because, all pio lines are also configured as inputs and have internal pull-down resistors, any unconnected pio lines will cause a pwm trip. therefore, prior to using the pwm system of the admc401, it is imperative that the pio stage be correctly configured for the particular application. 8.6 pio r egisters the configuration of all registers associated with the pio system of the admc401 are shown in graphically in figure 28 . each of the registers has a bit associated directly with one of the pio lines. for example, bit 0 of all registers affects only the pio0 line of the admc401.
a a admc401 - p reliminary t echnical i nformation a analog devices inc., proprietary & confidential 6/5/98 rev 2.1 - information subject to change page 64 of 74 piolevel (r/w) dm (0x2040) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 = falling edge (piomode = 0) = active low (piomode = 1) 1 = rising edge (piomode = 0) = active high (piomode = 1) piomode (r/w) dm (0x2041) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 = edge sensitive 1 = level sensitive piopwm (r/w) dm (0x2042) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 1 1 1 1 1 1 1 1 1 1 1 0 = pwm trip disable 1 = pwm trip enable piodir (r/w) dm (0x2044) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 = input 1 = output piodata (r/w) dm (0x2045) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 = lo level 1 = hi level piointen (r/w) dm (0x2046) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 = interrupt disable 1 = interrupt enable pioflag (r) dm (0x2047) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 = no interrupt 1 = interrupt flagged figure 28 : structure of pio registers of admc401.
a a admc401 - p reliminary t echnical i nformation a analog devices inc., proprietary & confidential 6/5/98 rev 2.1 - information subject to change page 65 of 74 9. 0 event timers 9. 1 o verview the admc401 contains a dual channel event timer unit (etu) that may be used to accurately measure the elapsed time between defined instants on a particular channel. the etu has two dedicated input pins, etu0 and etu1. the etu system contains a set of 16-bit data registers that are used to store the value of the dedicated etu timer on the occurrence of defined events on the input pins. a configuration register is used to define the nature of the events on each of the input pins. in addition, a control register is used to initiate event capture on the inputs. a status register may be read to determine the state of the two capture channels. a dedicated etu interrupt may be generated upon completion of a capture sequence on either the etu0 or etu1 channels. an event may be defined as either a rising or falling edge on the associated etu0 and etu1 inputs pins. therefore, the etu system can be used to compute the frequency, period, duty cycle or on-time of signals applied at the inputs. a block diagram of the etu system of the admc401 is shown in figure 29 . event detector etu0 etua0 (0-15) etub0 (0-15) etuaa0 (0-15) event detector etu1 etua1 (0-15) etub1 (0-15) etuaa1 (0-15) etudivide (0-15) etu timer clkout etuconfig (0-7) etuctrl (0-1) etustat (0-1) etu interrupt etu channel 0 etu channel 1 etutime (0-15) figure 29 : functional block diagram of event timer unit of admc401. 9.2 etu e vent d efinition the etu system of the admc401 contains a dedicated 16-bit timer whose clock frequency may be programmed using the etudivide register. this register divides the clkin frequency to provide the clock signal for the etu timer. the clock
a a admc401 - p reliminary t echnical i nformation a analog devices inc., proprietary & confidential 6/5/98 rev 2.1 - information subject to change page 66 of 74 frequency of the etu timer may be expressed as clkin/etudivide and is common to both channels. at any time, the contents of the etu timer may be read in the 16-bit read only etutime register. there are two events that are used to trigger the etu, termed event a and event b. by setting the appropriate bits of the etuconfig register, it is possible to define both events a and b as either rising or falling edges on the appropriate pin. for example, setting bit 0 of the etuconfig register, defines event a of the etu0 channel as a rising edge on the etu0 pin. similarly, setting bit 4 of the etuconfig register defines event a of the etu1 channel as a rising edge on the etu1 pin. event a defines the start of the event capture sequence. associated with each etu channel are three data registers, etua0, etub0 and etuaa0 for etu channel 0 and etua1, etub1 and etuaa1 for etu channel 1. these data registers store the etu timer value on the occurrence of the first a event, the first b event and the second a event respectively. for example, for etu channel 0, etua0 store the timer value on the first occurrence of event a on the etu0 pin, etub0 stores the timer value on the first occurrence of event b on the etu0 pin and etuaa0 store the timer value on the second occurrence of event a on the etu0 pin. registers etua1, etub1 and etuaa1 perform the same function for events on etu channel 1. 9.3 etu i nterrupt g eneration the completion of the event capture sequence can be defined as either the occurrence of event b or the second occurrence of event a by setting the appropriate bits of the etuconfig register. at the end of the capture sequence, the etu generates an interrupt. for example, if bit 2 of the etuconfig register is set, etu channel 0 will generate an etu interrupt on the occurrence of event b on the etu0 pin. on the other hand, if bit 6 of the etuconfig register is cleared, etu channel 1 will generate an etu interrupt on the occurrence of the second event a on the etu1 pin. both etu channels generate the same interrupt to the dsp when capture is complete. if both etu channels are used simultaneously, the etustat register can be polled to determine the status of both channels and determine which caused the interrupt. if capture on etu channel 0 is complete, bit 0 of the etustat register is set. similarly, if event capture on etu channel 1 is complete, bit 1 of the etustat register is set. reading the etustat register automatically clears all bits of the register. 9.4 etu o perating m odes the etu channels of the admc401 can operate in two distinct modes; single shot and free-running. the particular mode may be selected for etu channel 0 by programming bit 3 of the etuconfig register and for etu channel 1 by programming bit 7 of the etuconfig register. setting these bits puts the respective etu channel in free-running mode while clearing the bits enables the single-shot mode. in single-shot mode, upon completion of the capture sequence and consequent generation of the interrupt, further event capture is disabled until the interrupt has been serviced and the appropriate bit of the etuctrl register has been set. setting bit 0 of the etuctrl register restarts the capture for etu channel 0, while bit 1 restarts capture for channel 1. in the free-running mode, the bits of the etuctrl register remain set and the etu channel continues to capture following the generation of the interrupt. 9.5 etu r egisters the configuration of the etu registers are summarized graphically in figure 30 .
a a admc401 - p reliminary t echnical i nformation a analog devices inc., proprietary & confidential 6/5/98 rev 2.1 - information subject to change page 67 of 74 dm (0x2050) - dm(0x2056) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 etua0 (r) etub0 (r) etuaa0 (r) etua1 (r) etub1 (r) etuaa1 (r) etutime (r) dm (0x205c) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 etuconfig (r/w) etu0 event a 0 = falling edge 1 = rising edge etu0 event b 0 = falling edge 1 = rising edge etu0 interrupt 0 = next event a 1 = event b etu0 mode 0 = single-shot 1 = free-running etu1 event a 0 = falling edge 1 = rising edge etu1 event b 0 = falling edge 1 = rising edge etu1 interrupt 0 = next event a 1 = event b etu1 mode 0 = single-shot 1 = free-running dm (0x205d) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 etudivide (r/w) dm (0x205e) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 etustat (r) etu0 0 = not captured 1 = sequence captured etu1 0 = not captured 1 = sequence captured dm (0x205f) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 etuctrl (r/w) etu0 0 = do not start 1 = start capture etu1 0 = do not capture 1 = start capture figure 30 : configuration of etu registers.
a a admc401 - p reliminary t echnical i nformation a analog devices inc., proprietary & confidential 6/5/98 rev 2.1 - information subject to change page 68 of 74 10. auxiliary pwm timers the admc401 provides two auxiliary, fixed-frequency, variable duty cycle pwm outputs that may be used to drive auxiliary switching circuits in the motor control system. alternatively, by adding appropriate filtering at the output these signals can be used as to provide a simple digital-to-analog converter. these output signals appear on the aux0 and aux1 pins and are controlled by the duty cycle registers, auxtim0 and auxtim1. the auxiliary pwm outputs operate at a fixed frequency that is clkin/256. this give an auxiliary pwm switching frequency of 50.7 khz for a 13 mhz clkin. the output duty cycle at the auxiliary pwm output pin is controlled by comparing the 8-bit auxiliary pwm duty-cycle registers, auxtim0 and auxtim1 with the contents of a timer. the value written to these registers may range from 0 to 255 so that duty-cycles from 0 to 99.6% may be produced at the output pins. a simple filter at the output could then be used to produce a corresponding analog output from 0 to 4.98 v. the outputs of the two auxiliary pwm timer circuits are synchronized on their rising edges. when the auxiliary timer registers are written to the value becomes effective immediately. therefore, if the value is smaller than the present timer value, the outputs go low immediately. the correct duty cycle appears for the subsequent auxiliary pwm period. on reset, the auxtim0 and auxtim1 registers are cleared so that no auxiliary pwm signals are produced and the aux0 and aux1 pins are low until these registers are programmed. the format of the auxtim0 and auxtim1 registers is shown in figure 31 . dm (0x2010) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 auxtim0 (w) dm (0x2011) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 auxtim1 (w) aux0 duty cycle = auxtim0/256 aux1 duty cycle = auxtim1/256 figure 31 : configuration of auxiliary pwm timer registers 11 watchdog timer 11.1o verview the watchdog timer is used as a protection mechanism against unintentional software events causing the dsp to become stuck in infinite loops. it can be used to cause a compete dsp and peripheral reset in the event of such a software error. the watchdog timer consists of a 16-bit timer that is clocked at the clkin rate, t cki . in fact, for increased ruggedness of the watchdog timer circuit, a separate clock signal is derived directly from the crystal or oscillator inputs just for the watchdog circuit. the watchdog timer is disabled on power up. the watchdog timer is enabled by writing a timeout value to the wdtimer register. this also resets the wdflag in the sysstat register. once the watchdog timer has been initialized, the contents of the timer are decremented at the clkin rate. in order to prevent a watchdog timer trip, it is
a a admc401 - p reliminary t echnical i nformation a analog devices inc., proprietary & confidential 6/5/98 rev 2.1 - information subject to change page 69 of 74 necessary to write again to the wdtimer register. for all writes to the wdtimer register (subsequent to the initial write), it is unimportant what value is written. the act of writing to the wdtimer register automatically reloads the initial timeout value. if the watchdog timer is not re-written to after an interval: t wdtimer t wdt cki = the watchdog timer will decrement to zero and a watchdog trip will be generated. in this case a complete reset of the dsp core and motor control peripherals is initiated and bit 1 of the sysstat register (wdflag) is set. following the reset, the dsp core can determine if the reset was caused by a watchdog trip (and so take appropriate action) or if it is due to the normal power up or reset sequence. the watchdog timer remains disabled while the wdflag is set to prevent continuous watchdog trips. the watchdog timer can be restarted and the wdflag reset by writing a nonzero timeout ? value to the wdtimer register. the wdflag will be reset but the watchdog timer will remain disabled if 0x0000 is written to the wdtimer register. the watchdog timer is reset by an asynchronous low input on the reset line. the watchdog circuit is not reset by the general peripheral reset (by calling the per_rst rom utility or toggling the fl2 flag). 12 programmable interrupt controller. 12.1 o verview the admc401 uses the irq2 pin of the dsp core to generate a peripheral interrupt. there are multiple sources of peripheral interrupts e.g. the adc block, pio block, eiu block, etu block and pwm block. to avoid a software latency in determining the source of the interrupt a programmable interrupt controller (pic) is used. the pic block essentially augments the existing adsp2171 vector table with additional vector addresses, one address for each of the eleven new interrupt sources. with the occurrence of an interrupt from the peripheral blocks, the pic block generates an address which points to the corresponding vector address in the dsp vector table. the pic consists of an output register, picvector. the contents of this register contain a pointer to an entry in the dsp vector table. during normal operation the interrupt service routine (isr) located at vector address 0x0004 (or the irq2 /peripheral interrupt) jumps to the address pointed to by the picvector register. the vector addresses between 0x00 and 0x2c are reserved for the dsp core interrupts. the vector table addresses from pm(0x30) to pm(0x58) are reserved for use by peripheral interrupt service routines. each vector address occupies four addresses of pm. the size of the picvector from the dsp prospective is 16 bits, however only five of these bits are necessary to cover the range of addresses. the priority of the peripheral interrupts is fixed in hardware. the isr at address pm(0x30) has the highest priority while the isr at address pm(0x58) has the lowest. in the case of multiple simultaneous interrupts, the pic will load the picvector register with the interrupt that has the highest priority. in between reads of the picvector register (while the dsp is servicing other interrupts for example) the picvector is updated with the highest priority of any peripheral interrupts. this ensures that when the irq2 is again re- asserted, the highest priority interrupt that occurred since the last reading of the picvector register is now waiting to be serviced. note that in normal operation the irq2 isr should disable interrupts and then jump to the address pointed to by the picvector register. the onus is on the subsequent peripheral isr to re-enable interrupts early on in the isr if desired. the pic block will assert a new interrupt only after the picvector register has been read. the dsp will respond to the interrupt only after interrupts have been re-enabled on irq2 . when picvector is read, if another interrupt is pending in
a a admc401 - p reliminary t echnical i nformation a analog devices inc., proprietary & confidential 6/5/98 rev 2.1 - information subject to change page 70 of 74 the pic, then the irq2 line to the dsp remains lo and no edge will be seen. in order to catch all interrupts, irq2 interrupts should be configured as level sensitive in the icntl register. the four least significant pio pins are assigned unique vector addresses. an interrupt on any of the remaining eight lines (pio4 to pio11) will trigger a separate fifth pio interrupt that has its own vector address. the pioflag register can be read to determine the exact source of this fifth interrupt. an 11-bit picmask register can be used to enable or disable any or all of the eleven peripheral interrupt sources. 12.2 pic r egisters the program memory addresses of the vector table reserved for the various peripheral interrupts are summarized in table 10 . the picmask register is described in figure 32 . pm address function 0x30 adc end of conversion interrupt 0x34 pwmsync interrupt 0x38 eiu loop timer time out interrupt 0x3c pio4 to pio11 interrupt 0x40 eiu counter error interrupt 0x44 etu interrupt 0x48 pio0 interrupt 0x4c pio1 interrupt 0x50 pio2 interrupt 0x54 pio3 interrupt 0x58 pwm trip interrupt table 10 : peripheral interrupt vector address table. picmask (r/w) dm (0x201d) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 pwmsync adc end of conversion eiu loop timer timeout pio4 - pio11 interrupt etu interrupt pwm trip interrupt eiu count error interrupt pio3 interrupt pio2 interrupt pio1 interrupt pio0 interrupt 0 = disable interrupt (mask) 1 = enable interrupt figure 32 : structure of picmask register of admc401.
a a admc401 - p reliminary t echnical i nformation a analog devices inc., proprietary & confidential 6/5/98 rev 2.1 - information subject to change page 71 of 74 13. 0 system controller. 13. 1 o verview the system controller has a number of functions: 1. it decodes the dsp address bus and selects the appropriate peripheral registers. 2. it controls the sport1 multiplexer select lines. 3. it resets the peripherals and control registers on hardware, software or watchdog initiated resets. 4. it can be used to control the peripheral test modes. 13. 2 dsp interface and m emory m ap all data transfer between the dsp core and the peripherals is controlled by the system controller. when the dsp core puts a valid peripheral address on the dm address bus, the system controller generates an active low chip select signal for the selected peripheral register. if the resister is a read only register data will be loaded onto the dsp dm data bus only on the rising edge of rd . conversely, if the resister is a write register, data will be loaded into the register only on the rising edge of wr . the peripheral registers are right justified, i.e. the lsb of each register is connected to the lsb of the 16 bit dsp dm data bus. any unused bits are connected to a logic zero. the admc401 peripheral registers are memory mapped to the dsp data address space, starting at address 0x2000. the peripheral registers are summarized in table 11 . address name type bits reset value function 0x2000 - 0x2007 reserved 0x2008 pwmtm r/w 15:0 0x0000 pwm period register 0x2009 pwmdt r/w 9:0 0x0000 pwm deadtime register 0x200a pwmpd r/w 9:0 0x0000 pwm pulse deletion register 0x200b pwmgate r/w 9:0 0x0000 pwm chopping control 0x200c pwmcha r/w 15:0 undefined pwm channel a duty cycle control 0x200d pwmchb r/w 15:0 undefined pwm channel b duty cycle control 0x200e pwmchc r/w 15:0 undefined pwm channel c duty cycle control 0x200f pwmseg r/w 8:0 0x000 pwm crossover & output enable 0x2010 auxtim0 w 7:0 undefined aux. pwm channel 0 duty cycle 0x2011 auxtim1 w 7:0 undefined aux. pwm channel 1 duty cycle 0x2012 - 0x2014 reserved 0x2015 modectrl r/w 6:4 0x00 mode control register 0x2016 sysstat r 4:0 undefined system status register 0x2017 reserved 0x2018 wdtimer r/w 15:0 undefined watchdog timer register 0x2019 - 0x201b reserved 0x201c picvector r 15:0 undefined peripheral interrupt address 0x201d picmask r/w 10:0 0x000 peripheral interrupt mask register 0x201e - 0x201f reserved 0x2020 eiucnt r/w 15:0 0x0000 position count value 0x2021 eiumaxcnt r/w 15:0 0x0000 maximum eiucnt value 0x2022 eiustat r 6:0 undefined eiu status register 0x2023 eiuctrl r/w 8:0 0x00 eiu control register
a a admc401 - p reliminary t echnical i nformation a analog devices inc., proprietary & confidential 6/5/98 rev 2.1 - information subject to change page 72 of 74 0x2024 eiuperiod r/w 15:0 0x0000 eiu loop timer period register 0x2025 eiuscale r/w 7:0 0x00 eiu loop timer scale register 0x2026 eiutimer r/w 15:0 0x0000 eiu loop timer register 0x2027 eetcnt r 15:0 0x0000 latched copy of eiucnt 0x2028 eiufilter r/w 5:0 0x0 eiu filter control register 0x2029 eizplatch r 15:0 undefined zp1 latch register 0x202a eislatch r 15:0 undefined zp2 latch register 0x202b - 0x202f reserved 0x2030 adc1 r 15:0 undefined adc1 data register 0x2031 adc2 r 15:0 undefined adc2 data register 0x2032 adc3 r 15:0 undefined adc3 data register 0x2033 adc4 r 15:0 undefined adc4 data register 0x2034 adc5 r 15:0 undefined adc5 data register 0x2035 adc6 r 15:0 undefined adc6 data register 0x2036 adc7 r 15:0 undefined adc7 data register 0x2037 adc8 r 15:0 undefined adc8 data register 0x2038 adcctrl r/w 3:0 0x08 adc control register 0x2039 adcstat r 0 undefined adc status register 0x203a adctest r/w 3:0 0x0 adc channel select register 0x203b - 0x203f reserved 0x2040 piolevel r/w 11:0 0x0000 pio interrupt select 0x2041 piomode r/w 11:0 0x0000 pio interrupt edge/level select 0x2042 piopwm r/w 11:0 0x0fff pio pwmtrip enable register 0x2043 reserved 0x2044 piodir r/w 11:0 0x0000 pio direction control 0x2045 piodata r/w 11:0 undefined pio data register 0x2046 piointen r/w 11:4 0x0000 pio interrupt enable 0x2047 pioflag r 11:4 undefined pio interrupt flag (pio4 to pio11) 0x2048 - 0x204f reserved 0x2050 etua0 r 15:0 undefined event a capture - channel 0 0x2051 etub0 r 15:0 undefined event b capture - channel 0 0x2052 etuaa0 r 15:0 undefined event aa capture - channel 0 0x2053 etua1 r 15:0 undefined event a capture - channel 1 0x2054 etub1 r 15:0 undefined event b capture - channel 1 0x2055 etuaa1 r 15:0 undefined event aa capture - channel 1 0x2056 etutime r 15:0 undefined etu timer value 0x205c etuconfig r/w 7:0 0x00 etu configuration register 0x205d etudivide r/w 15:0 0x0000 etu clock divide register 0x205e etustat r 1:0 undefined etu status register 0x205f etuctrl r/w 1:0 0x0 etu control register 0x2060 pwmsyncwt r/w 7:0 0x27 pwmsync width control 0x2061 pwmswt r/w 0 0x0 pwm software trip 0x2062 - 0x206f reserved 0x2070 eetn r/w 7:0 0x00 eet pulse decimator register 0x2071 eetdiv r/w 15:0 0x0000 eet clock divider register
a a admc401 - p reliminary t echnical i nformation a analog devices inc., proprietary & confidential 6/5/98 rev 2.1 - information subject to change page 73 of 74 0x2072 eetdeltat r 15:0 0x0000 eet timer period register 0x2073 eett r 15:0 0x0000 eet delta timer register 0x2074 eetstat r 0 0x0 eet status register 0x2075 - 0x23ff reserved table 11 : peripheral registers of admc401 13. 3 modectrl r egister the sport1 peripheral pins are configured using the modectrl register. two bits of this register control the sport1 uart and dr1a/dr1b multiplexer. setting the uarten bit connects dr1a to the rfs1 input which allows sport1 to be used as a uart port. the dr1sel bit selects either pins dr1a or dr1b. the reset condition for all bits in this register is zero. setting the uarten bit will also multiplex the fl1 pin on the adsp2171 core to the rfs1 pin on the admc401. in this mode this pin is called srom and is used to reset the srom. the structure of the sport1 multiplex and control lines is shown in figure 33 . 2171 sport1 uart enable dt1 dr1a dr1b tfs1 rfs1 sclck1 dt1 dr1 tfs1 sclck1 rfs1 dr1b select default switch positions shown 2171::fl1 figure 33 : sport1 and srom multiplexer. additionally, setting bit 6 of the modectrl register places the pwm in the double update mode. clearing the bit places the pwm in the single update mode. bit 6 is cleared by default on power up or following a reset. 13.4 sysstat r egister the sysstat register indicates various status information of the admc401 such as: 1. the status of the pwmtrip pin. 2. the status of the watchdog flag 3. the status of the pwmpol pin 4. the phase of the pwm 5. the status of the sr mode of the pwm 13.5 s ystem c ontroller i nterface & r egisters the registers of the system control block are illustrated in figure 34 .
a a admc401 - p reliminary t echnical i nformation a analog devices inc., proprietary & confidential 6/5/98 rev 2.1 - information subject to change page 74 of 74 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 sysstat (r) dm (0x2016) pwmpol pin state 1=hi => active hi 0=lo => active lo 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 modectrl (r/w) dm (0x2015) 0 0 0 data receive select 1=dr1b 0=dr1a sport1 mode 1=uart mode 0=sport mode pwm mode 1=double update 0=single update pwmtrip pin state 1=hi 0=lo watchdog flag 1=watchdog trip 0=no watchdogtrip pwm sr mode 1=> sr mode disabled 0=> sr mode enabled pwm phase flag 1=second half cycle 0=first half cycle figure 34 : configuration of modectrl and sysstat registers of admc401.

▲Up To Search▲

Price & Availability of DS1991

	To Download DS1991 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .